EDN Simulation Results

Tuesday May 27 2025 18:36:03 UTC

GitHub Revision: 872a98e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.700s	27.636us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.700s	42.861us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.700s	20.794us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.510s	380.465us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	2.140s	131.039us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.730s	39.393us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.700s	20.794us	1	1	100.00
		edn_csr_aliasing	2.140s	131.039us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	1.970s	64.981us	1	1	100.00
V2	csrng_commands	edn_genbits	1.970s	64.981us	1	1	100.00
V2	genbits	edn_genbits	1.970s	64.981us	1	1	100.00
V2	interrupts	edn_intr	1.800s	41.098us	1	1	100.00
V2	alerts	edn_alert	1.990s	90.297us	1	1	100.00
V2	errs	edn_err	1.830s	29.458us	1	1	100.00
V2	disable	edn_disable	1.760s	11.199us	1	1	100.00
		edn_disable_auto_req_mode	2.020s	41.580us	1	1	100.00
V2	stress_all	edn_stress_all	2.530s	145.466us	1	1	100.00
V2	intr_test	edn_intr_test	1.750s	18.063us	1	1	100.00
V2	alert_test	edn_alert_test	2.360s	136.915us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.520s	232.008us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.520s	232.008us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.700s	42.861us	1	1	100.00
		edn_csr_rw	1.700s	20.794us	1	1	100.00
		edn_csr_aliasing	2.140s	131.039us	1	1	100.00
		edn_same_csr_outstanding	1.820s	88.452us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.700s	42.861us	1	1	100.00
		edn_csr_rw	1.700s	20.794us	1	1	100.00
		edn_csr_aliasing	2.140s	131.039us	1	1	100.00
		edn_same_csr_outstanding	1.820s	88.452us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	8.420s	1.103ms	1	1	100.00
		edn_tl_intg_err	2.460s	58.730us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.750s	34.631us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.990s	90.297us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	8.420s	1.103ms	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	8.420s	1.103ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	8.420s	1.103ms	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	8.420s	1.103ms	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.990s	90.297us	1	1	100.00
		edn_sec_cm	8.420s	1.103ms	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.990s	90.297us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.460s	58.730us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	37.340s	40.362ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00