HMAC Simulation Results

Tuesday May 27 2025 18:36:03 UTC

GitHub Revision: 872a98e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 9.960s 1.094ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.790s 74.169us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.840s 17.408us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 12.070s 4.142ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 3.540s 832.370us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 2.460s 70.807us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.840s 17.408us 1 1 100.00
hmac_csr_aliasing 3.540s 832.370us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 48.760s 16.690ms 1 1 100.00
V2 back_pressure hmac_back_pressure 14.340s 289.386us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.990s 1.088ms 1 1 100.00
hmac_test_sha384_vectors 19.440s 2.237ms 1 1 100.00
hmac_test_sha512_vectors 19.210s 464.807us 1 1 100.00
hmac_test_hmac256_vectors 8.320s 226.027us 1 1 100.00
hmac_test_hmac384_vectors 10.830s 993.143us 1 1 100.00
hmac_test_hmac512_vectors 14.050s 354.020us 1 1 100.00
V2 burst_wr hmac_burst_wr 14.260s 757.117us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 8.482m 4.022ms 1 1 100.00
V2 error hmac_error 1.230m 16.014ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 53.690s 2.848ms 1 1 100.00
V2 save_and_restore hmac_smoke 9.960s 1.094ms 1 1 100.00
hmac_long_msg 48.760s 16.690ms 1 1 100.00
hmac_back_pressure 14.340s 289.386us 1 1 100.00
hmac_datapath_stress 8.482m 4.022ms 1 1 100.00
hmac_burst_wr 14.260s 757.117us 1 1 100.00
hmac_stress_all 3.220m 32.496ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 9.960s 1.094ms 1 1 100.00
hmac_long_msg 48.760s 16.690ms 1 1 100.00
hmac_back_pressure 14.340s 289.386us 1 1 100.00
hmac_datapath_stress 8.482m 4.022ms 1 1 100.00
hmac_wipe_secret 53.690s 2.848ms 1 1 100.00
hmac_test_sha256_vectors 8.990s 1.088ms 1 1 100.00
hmac_test_sha384_vectors 19.440s 2.237ms 1 1 100.00
hmac_test_sha512_vectors 19.210s 464.807us 1 1 100.00
hmac_test_hmac256_vectors 8.320s 226.027us 1 1 100.00
hmac_test_hmac384_vectors 10.830s 993.143us 1 1 100.00
hmac_test_hmac512_vectors 14.050s 354.020us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 9.960s 1.094ms 1 1 100.00
hmac_long_msg 48.760s 16.690ms 1 1 100.00
hmac_back_pressure 14.340s 289.386us 1 1 100.00
hmac_datapath_stress 8.482m 4.022ms 1 1 100.00
hmac_burst_wr 14.260s 757.117us 1 1 100.00
hmac_error 1.230m 16.014ms 1 1 100.00
hmac_wipe_secret 53.690s 2.848ms 1 1 100.00
hmac_test_sha256_vectors 8.990s 1.088ms 1 1 100.00
hmac_test_sha384_vectors 19.440s 2.237ms 1 1 100.00
hmac_test_sha512_vectors 19.210s 464.807us 1 1 100.00
hmac_test_hmac256_vectors 8.320s 226.027us 1 1 100.00
hmac_test_hmac384_vectors 10.830s 993.143us 1 1 100.00
hmac_test_hmac512_vectors 14.050s 354.020us 1 1 100.00
hmac_stress_all 3.220m 32.496ms 1 1 100.00
V2 stress_all hmac_stress_all 3.220m 32.496ms 1 1 100.00
V2 alert_test hmac_alert_test 1.510s 34.040us 1 1 100.00
V2 intr_test hmac_intr_test 1.620s 16.130us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 4.140s 208.547us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 4.140s 208.547us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.790s 74.169us 1 1 100.00
hmac_csr_rw 1.840s 17.408us 1 1 100.00
hmac_csr_aliasing 3.540s 832.370us 1 1 100.00
hmac_same_csr_outstanding 3.070s 337.623us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.790s 74.169us 1 1 100.00
hmac_csr_rw 1.840s 17.408us 1 1 100.00
hmac_csr_aliasing 3.540s 832.370us 1 1 100.00
hmac_same_csr_outstanding 3.070s 337.623us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.830s 125.640us 1 1 100.00
hmac_tl_intg_err 4.470s 943.926us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 4.470s 943.926us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 9.960s 1.094ms 1 1 100.00
V3 stress_reset hmac_stress_reset 4.230s 296.084us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.846m 3.067ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.920s 666.882us 1 1 100.00
TOTAL 28 28 100.00