I2C Simulation Results

Tuesday May 27 2025 18:36:03 UTC

GitHub Revision: 872a98e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	13.710s	2.594ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	7.860s	2.627ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.530s	18.900us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.560s	19.148us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.220s	455.854us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.150s	147.003us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.880s	89.445us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.560s	19.148us	1	1	100.00
		i2c_csr_aliasing	2.150s	147.003us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	1.870s	162.358us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	15.444m	111.583ms	1	1	100.00
V2	host_maxperf	i2c_host_perf	9.110s	303.983us	1	1	100.00
V2	host_override	i2c_host_override	1.590s	92.224us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	3.407m	4.617ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	31.650s	7.684ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.050s	98.048us	1	1	100.00
		i2c_host_fifo_fmt_empty	10.950s	615.164us	1	1	100.00
		i2c_host_fifo_reset_rx	5.380s	2.690ms	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	2.104m	3.108ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	21.580s	1.526ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.730s	80.332us	1	1	100.00
V2	target_glitch	i2c_target_glitch	6.810s	8.420ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	1.257m	13.720ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.340s	4.837ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	35.850s	3.601ms	1	1	100.00
		i2c_target_intr_smoke	6.140s	1.453ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.200s	188.665us	1	1	100.00
		i2c_target_fifo_reset_tx	2.060s	232.103us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	5.684m	43.961ms	1	1	100.00
		i2c_target_stress_rd	35.850s	3.601ms	1	1	100.00
		i2c_target_intr_stress_wr	1.521m	10.870ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.380s	5.069ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	2.790s	312.917us	1	1	100.00
V2	bad_address	i2c_target_bad_addr	2.960s	444.320us	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.330s	263.967us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	3.080s	1.114ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.910s	131.356us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	9.110s	303.983us	1	1	100.00
		i2c_host_perf_precise	2.120s	279.953us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	21.580s	1.526ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	3.380s	218.092us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.680s	1.488ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.490s	2.076ms	1	1	100.00
		i2c_target_nack_txstretch	2.410s	138.729us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	5.130s	498.367us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.840s	528.924us	1	1	100.00
V2	alert_test	i2c_alert_test	1.560s	15.986us	1	1	100.00
V2	intr_test	i2c_intr_test	1.450s	52.176us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.440s	42.594us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.440s	42.594us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.530s	18.900us	1	1	100.00
		i2c_csr_rw	1.560s	19.148us	1	1	100.00
		i2c_csr_aliasing	2.150s	147.003us	1	1	100.00
		i2c_same_csr_outstanding	1.840s	52.002us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.530s	18.900us	1	1	100.00
		i2c_csr_rw	1.560s	19.148us	1	1	100.00
		i2c_csr_aliasing	2.150s	147.003us	1	1	100.00
		i2c_same_csr_outstanding	1.840s	52.002us	1	1	100.00
V2		TOTAL			38	38	100.00
V2S	tl_intg_err	i2c_tl_intg_err	1.900s	96.565us	1	1	100.00
		i2c_sec_cm	1.660s	45.361us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.900s	96.565us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	8.630s	1.778ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.900s	452.050us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	9.550s	1.795ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			47	50	94.00

Failure Buckets

• UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.26823864387981952399629403924941237050840816731356983841650935309249338606942
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 452050243 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 452050243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.50321545199707911262810301712590714812580673706864369453705604790348261282105
      Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1778459698 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1778459698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.47610325942786689175801225319622355775598879373865345177641091632966609265310
      Line 111, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1794502154 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 202 [0xca])
        UVM_INFO @ 1794502154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---