KEYMGR Simulation Results

Tuesday May 27 2025 18:36:03 UTC

GitHub Revision: 872a98e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	3.830s	60.587us	1	1	100.00
V1	random	keymgr_random	4.090s	233.056us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.720s	18.064us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.750s	70.437us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	10.330s	1.809ms	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	5.070s	860.700us	0	1	0.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.540s	49.844us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.750s	70.437us	1	1	100.00
		keymgr_csr_aliasing	5.070s	860.700us	0	1	0.00
V1		TOTAL			6	7	85.71
V2	cfgen_during_op	keymgr_cfg_regwen	3.970s	57.430us	1	1	100.00
V2	sideload	keymgr_sideload	2.860s	93.003us	1	1	100.00
		keymgr_sideload_kmac	2.970s	114.504us	1	1	100.00
		keymgr_sideload_aes	2.690s	94.912us	1	1	100.00
		keymgr_sideload_otbn	4.950s	352.667us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	8.950s	1.881ms	1	1	100.00
V2	lc_disable	keymgr_lc_disable	3.610s	301.936us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.090s	137.546us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	4.540s	377.854us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	3.350s	94.654us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	3.100s	463.248us	1	1	100.00
V2	stress_all	keymgr_stress_all	25.160s	2.312ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.660s	46.873us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.920s	13.008us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.020s	129.380us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.020s	129.380us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.720s	18.064us	1	1	100.00
		keymgr_csr_rw	1.750s	70.437us	1	1	100.00
		keymgr_csr_aliasing	5.070s	860.700us	0	1	0.00
		keymgr_same_csr_outstanding	3.030s	855.120us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.720s	18.064us	1	1	100.00
		keymgr_csr_rw	1.750s	70.437us	1	1	100.00
		keymgr_csr_aliasing	5.070s	860.700us	0	1	0.00
		keymgr_same_csr_outstanding	3.030s	855.120us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	14.080s	1.145ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	14.080s	1.145ms	1	1	100.00
		keymgr_tl_intg_err	2.560s	117.733us	0	1	0.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.720s	798.510us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.720s	798.510us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.720s	798.510us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.720s	798.510us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	12.990s	479.045us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	14.080s	1.145ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	14.080s	1.145ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	2.560s	117.733us	0	1	0.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.720s	798.510us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	3.970s	57.430us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	4.090s	233.056us	1	1	100.00
		keymgr_csr_rw	1.750s	70.437us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	4.090s	233.056us	1	1	100.00
		keymgr_csr_rw	1.750s	70.437us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	4.090s	233.056us	1	1	100.00
		keymgr_csr_rw	1.750s	70.437us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	3.610s	301.936us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	3.350s	94.654us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	3.350s	94.654us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	4.090s	233.056us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	2.560s	175.262us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	14.080s	1.145ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	14.080s	1.145ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	14.080s	1.145ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	3.240s	238.111us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	3.610s	301.936us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	14.080s	1.145ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	14.080s	1.145ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	14.080s	1.145ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	3.240s	238.111us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	3.240s	238.111us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	14.080s	1.145ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	3.240s	238.111us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	14.080s	1.145ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	3.240s	238.111us	1	1	100.00
V2S		TOTAL			5	6	83.33
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	14.510s	2.793ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			28	30	93.33

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 2 failures:

  • Test keymgr_tl_intg_err has 1 failures.

    • 0.keymgr_tl_intg_err.10093103999676641704447103389563607581999011980287877218436455413497434231946
      Line 101, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[16] & 'hffffffff)))'
        UVM_ERROR @ 117732789 ps: (keymgr_csr_assert_fpv.sv:449) [ASSERT FAILED] attest_sw_binding_3_rd_A
        UVM_INFO @ 117732789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_aliasing has 1 failures.

    • 0.keymgr_csr_aliasing.13908615424928823845810421986267939626688873920340533989578044364485397717815
      Line 75, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_aliasing/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[16] & 'hffffffff)))'
        UVM_ERROR @ 860700163 ps: (keymgr_csr_assert_fpv.sv:449) [ASSERT FAILED] attest_sw_binding_3_rd_A
        UVM_INFO @ 860700163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---