KMAC/UNMASKED Simulation Results

Tuesday May 27 2025 18:36:03 UTC

GitHub Revision: 872a98e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	29.540s	890.564us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.030s	24.397us	1	1	100.00
V1	csr_rw	kmac_csr_rw	2.220s	68.816us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	10.950s	591.057us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.410s	1.512ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.270s	260.616us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.220s	68.816us	1	1	100.00
		kmac_csr_aliasing	8.410s	1.512ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.640s	17.137us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.870s	69.875us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	11.564m	28.768ms	1	1	100.00
V2	burst_write	kmac_burst_write	4.288m	51.498ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	30.120s	1.797ms	1	1	100.00
		kmac_test_vectors_sha3_256	17.869m	17.722ms	1	1	100.00
		kmac_test_vectors_sha3_384	13.124m	86.164ms	1	1	100.00
		kmac_test_vectors_sha3_512	9.425m	9.418ms	1	1	100.00
		kmac_test_vectors_shake_128	2.309m	9.830ms	1	1	100.00
		kmac_test_vectors_shake_256	17.809m	67.034ms	1	1	100.00
		kmac_test_vectors_kmac	2.580s	101.296us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.900s	1.344ms	1	1	100.00
V2	sideload	kmac_sideload	8.380s	760.654us	1	1	100.00
V2	app	kmac_app	2.356m	17.476ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.190m	10.543ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	3.454m	38.946ms	1	1	100.00
V2	error	kmac_error	2.944m	35.174ms	1	1	100.00
V2	key_error	kmac_key_error	5.420s	5.721ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	4.480s	410.444us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	20.100s	1.496ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	18.520s	1.527ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	27.740s	4.449ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.160s	51.684us	1	1	100.00
V2	stress_all	kmac_stress_all	8.516m	10.002ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.610s	43.587us	1	1	100.00
V2	alert_test	kmac_alert_test	1.930s	37.253us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.840s	65.977us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.840s	65.977us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.030s	24.397us	1	1	100.00
		kmac_csr_rw	2.220s	68.816us	1	1	100.00
		kmac_csr_aliasing	8.410s	1.512ms	1	1	100.00
		kmac_same_csr_outstanding	2.510s	170.219us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.030s	24.397us	1	1	100.00
		kmac_csr_rw	2.220s	68.816us	1	1	100.00
		kmac_csr_aliasing	8.410s	1.512ms	1	1	100.00
		kmac_same_csr_outstanding	2.510s	170.219us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.300s	68.160us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.300s	68.160us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.300s	68.160us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.300s	68.160us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.240s	105.136us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	46.270s	20.370ms	1	1	100.00
		kmac_tl_intg_err	1.790s	10.815us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.790s	10.815us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.160s	51.684us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	29.540s	890.564us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.380s	760.654us	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.300s	68.160us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	46.270s	20.370ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	46.270s	20.370ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	46.270s	20.370ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	29.540s	890.564us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.160s	51.684us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	46.270s	20.370ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.550m	8.756ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	29.540s	890.564us	1	1	100.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.303m	15.592ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: * has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.65351558641455246765176497231295990373987585735222909250878635842030906123495
      Line 85, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

        UVM_ERROR @ 105136495 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (547098314 [0x209c0eca] vs 2229870028 [0x84e91dcc]) Regname: kmac_reg_block.prefix_0 reset value: 0x0
        UVM_INFO @ 105136495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.100678477517287120633116483646746399223967530323857415335294151559456444838930
      Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[39] & 'hffffffff)))'
        UVM_ERROR @  10814708 ps: (kmac_csr_assert_fpv.sv:495) [ASSERT FAILED] prefix_0_rd_A
        UVM_INFO @  10814708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---