ROM_CTRL/32KB Simulation Results

Tuesday May 27 2025 18:36:03 UTC

GitHub Revision: 872a98e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 5.070s 627.290us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 4.460s 379.661us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 4.200s 131.408us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 4.510s 302.814us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 3.650s 385.934us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 4.660s 598.847us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 4.200s 131.408us 1 1 100.00
rom_ctrl_csr_aliasing 3.650s 385.934us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 4.130s 317.990us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 3.790s 499.256us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 4.820s 141.560us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 12.830s 474.820us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 6.890s 745.764us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.430s 304.722us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 6.690s 201.723us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 6.690s 201.723us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 4.460s 379.661us 1 1 100.00
rom_ctrl_csr_rw 4.200s 131.408us 1 1 100.00
rom_ctrl_csr_aliasing 3.650s 385.934us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.880s 164.965us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 4.460s 379.661us 1 1 100.00
rom_ctrl_csr_rw 4.200s 131.408us 1 1 100.00
rom_ctrl_csr_aliasing 3.650s 385.934us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.880s 164.965us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.798m 20.067ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 14.140s 1.042ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 1.495m 2.395ms 1 1 100.00
rom_ctrl_tl_intg_err 38.480s 1.394ms 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 1.495m 2.395ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 1.495m 2.395ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.798m 20.067ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.798m 20.067ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.798m 20.067ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.798m 20.067ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.798m 20.067ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 1.495m 2.395ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 1.495m 2.395ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 5.070s 627.290us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 5.070s 627.290us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 5.070s 627.290us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 38.480s 1.394ms 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.798m 20.067ms 1 1 100.00
rom_ctrl_kmac_err_chk 6.890s 745.764us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.798m 20.067ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.798m 20.067ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.798m 20.067ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 14.140s 1.042ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 1.495m 2.395ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.437m 22.334ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00