ROM_CTRL/64KB Simulation Results

Tuesday May 27 2025 18:36:03 UTC

GitHub Revision: 872a98e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 6.780s 755.476us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 7.780s 218.219us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 7.320s 309.462us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.210s 207.195us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 6.570s 2.090ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 5.880s 736.082us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 7.320s 309.462us 1 1 100.00
rom_ctrl_csr_aliasing 6.570s 2.090ms 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 7.170s 309.578us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 5.570s 650.517us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 6.640s 736.280us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 28.090s 2.148ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 11.610s 420.748us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 7.610s 287.464us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 12.020s 1.062ms 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 12.020s 1.062ms 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 7.780s 218.219us 1 1 100.00
rom_ctrl_csr_rw 7.320s 309.462us 1 1 100.00
rom_ctrl_csr_aliasing 6.570s 2.090ms 1 1 100.00
rom_ctrl_same_csr_outstanding 5.730s 756.123us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 7.780s 218.219us 1 1 100.00
rom_ctrl_csr_rw 7.320s 309.462us 1 1 100.00
rom_ctrl_csr_aliasing 6.570s 2.090ms 1 1 100.00
rom_ctrl_same_csr_outstanding 5.730s 756.123us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.259m 2.143ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 30.340s 1.071ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 5.231m 3.360ms 1 1 100.00
rom_ctrl_tl_intg_err 35.000s 1.058ms 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 5.231m 3.360ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 5.231m 3.360ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.259m 2.143ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.259m 2.143ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.259m 2.143ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.259m 2.143ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.259m 2.143ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 5.231m 3.360ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 5.231m 3.360ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 6.780s 755.476us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 6.780s 755.476us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 6.780s 755.476us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 35.000s 1.058ms 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.259m 2.143ms 1 1 100.00
rom_ctrl_kmac_err_chk 11.610s 420.748us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.259m 2.143ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.259m 2.143ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.259m 2.143ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 30.340s 1.071ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 5.231m 3.360ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.566m 7.535ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00