RV_DM/USE_JTAG_INTERFACE Simulation Results

Tuesday May 27 2025 18:36:03 UTC

GitHub Revision: 872a98e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 2.960s 498.627us 1 1 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 1.970s 552.204us 1 1 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 1.650s 173.797us 1 1 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 21.050s 37.571ms 1 1 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 3.010s 1.445ms 1 1 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 2.670s 1.666ms 1 1 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 5.130s 5.568ms 1 1 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 4.783m 152.804ms 1 1 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 1.201m 74.070ms 1 1 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 2.300s 567.328us 1 1 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 2.700s 888.620us 1 1 100.00
V1 cmderr_exception rv_dm_cmderr_exception 1.960s 369.528us 1 1 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 1.880s 260.882us 1 1 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 1.810s 271.739us 1 1 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 1.920s 1.118ms 1 1 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.530s 60.725us 1 1 100.00
V1 halt_resume rv_dm_halt_resume_whereto 1.770s 544.186us 1 1 100.00
V1 progbuf_busy rv_dm_cmderr_busy 2.300s 567.328us 1 1 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 1.800s 113.174us 1 1 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 2.680s 981.279us 1 1 100.00
V1 progbuf_exception rv_dm_cmderr_exception 1.960s 369.528us 1 1 100.00
V1 rom_read_access rv_dm_rom_read_access 1.670s 25.414us 1 1 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.320s 309.658us 1 1 100.00
V1 csr_rw rv_dm_csr_rw 2.040s 150.675us 1 1 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 39.430s 1.464ms 1 1 100.00
V1 csr_aliasing rv_dm_csr_aliasing 18.920s 2.878ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 1.540s 45.690us 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 18.920s 2.878ms 1 1 100.00
rv_dm_csr_rw 2.040s 150.675us 1 1 100.00
V1 mem_walk rv_dm_mem_walk 1.560s 62.278us 1 1 100.00
V1 mem_partial_access rv_dm_mem_partial_access 1.660s 58.402us 1 1 100.00
V1 TOTAL 26 27 96.30
V2 idcode rv_dm_smoke 2.960s 498.627us 1 1 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 1.790s 354.820us 1 1 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 2.140s 256.840us 1 1 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 1.670s 187.020us 1 1 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 2.110s 566.657us 1 1 100.00
V2 sba rv_dm_sba_tl_access 4.550s 1.836ms 1 1 100.00
rv_dm_delayed_resp_sba_tl_access 1.610s 80.016us 0 1 0.00
V2 bad_sba rv_dm_bad_sba_tl_access 10.800s 10.116ms 1 1 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 29.100s 15.499ms 1 1 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 1.900s 296.329us 1 1 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 2.750s 1.009ms 1 1 100.00
V2 ndmreset_req rv_dm_ndmreset_req 1.700s 313.314us 1 1 100.00
V2 hart_unavail rv_dm_hart_unavail 1.630s 137.803us 1 1 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 7.050s 7.808ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 2.260s 155.440us 0 1 0.00
V2 hartsel_warl rv_dm_hartsel_warl 1.590s 64.355us 1 1 100.00
V2 stress_all rv_dm_stress_all 8.950s 3.472ms 1 1 100.00
V2 alert_test rv_dm_alert_test 1.680s 41.966us 1 1 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 1.650s 32.836us 0 1 0.00
V2 tl_d_illegal_access rv_dm_tl_errors 1.650s 32.836us 0 1 0.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 18.920s 2.878ms 1 1 100.00
rv_dm_csr_hw_reset 2.320s 309.658us 1 1 100.00
rv_dm_csr_rw 2.040s 150.675us 1 1 100.00
rv_dm_same_csr_outstanding 6.270s 515.120us 1 1 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 18.920s 2.878ms 1 1 100.00
rv_dm_csr_hw_reset 2.320s 309.658us 1 1 100.00
rv_dm_csr_rw 2.040s 150.675us 1 1 100.00
rv_dm_same_csr_outstanding 6.270s 515.120us 1 1 100.00
V2 TOTAL 16 19 84.21
V2S tl_intg_err rv_dm_sec_cm 3.490s 3.059ms 1 1 100.00
rv_dm_tl_intg_err 6.490s 1.121ms 1 1 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 6.490s 1.121ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 2.750s 1.009ms 1 1 100.00
rv_dm_debug_disabled 1.870s 140.542us 1 1 100.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 2.750s 1.009ms 1 1 100.00
rv_dm_debug_disabled 1.870s 140.542us 1 1 100.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 2.960s 498.627us 1 1 100.00
V2S sec_cm_dm_en_ctrl_lc_gated rv_dm_buffered_enable 1.690s 174.812us 1 1 100.00
V2S sec_cm_sba_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.530s 54.748us 1 1 100.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.530s 54.748us 1 1 100.00
V2S sec_cm_exec_ctrl_mubi rv_dm_buffered_enable 1.690s 174.812us 1 1 100.00
V2S TOTAL 5 5 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 1.660s 147.831us 0 1 0.00
V3 TOTAL 0 1 0.00
Unmapped tests rv_dm_scanmode 1.600s 23.396us 1 1 100.00
TOTAL 48 53 90.57

Failure Buckets