RV_TIMER Simulation Results

Tuesday May 27 2025 18:36:03 UTC

GitHub Revision: 872a98e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.490s	35.466us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.540s	34.026us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.500s	26.890us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.610s	240.476us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.720s	331.595us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.520s	27.199us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.500s	26.890us	1	1	100.00
		rv_timer_csr_aliasing	1.720s	331.595us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.610s	72.466us	1	1	100.00
V2	disabled	rv_timer_disabled	2.070s	271.760us	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	1.320m	73.656ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	1.320m	73.656ms	1	1	100.00
V2	stress	rv_timer_stress_all	1.510s	25.975us	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.750s	41.927us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.560s	15.981us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.030s	74.019us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.030s	74.019us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.540s	34.026us	1	1	100.00
		rv_timer_csr_rw	1.500s	26.890us	1	1	100.00
		rv_timer_csr_aliasing	1.720s	331.595us	1	1	100.00
		rv_timer_same_csr_outstanding	1.570s	42.763us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.540s	34.026us	1	1	100.00
		rv_timer_csr_rw	1.500s	26.890us	1	1	100.00
		rv_timer_csr_aliasing	1.720s	331.595us	1	1	100.00
		rv_timer_same_csr_outstanding	1.570s	42.763us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.900s	62.433us	1	1	100.00
		rv_timer_tl_intg_err	2.260s	485.890us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.260s	485.890us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	11.310s	1.735ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.400s	15.055us	1	1	100.00
		rv_timer_max	1.560s	22.515us	1	1	100.00
		TOTAL			19	19	100.00