SPI_DEVICE/1R1W Simulation Results

Tuesday May 27 2025 18:36:03 UTC

GitHub Revision: 872a98e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	33.030s	7.594ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.020s	33.758us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.050s	36.282us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	8.700s	226.238us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	15.420s	14.321ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.760s	898.122us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.050s	36.282us	1	1	100.00
		spi_device_csr_aliasing	15.420s	14.321ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.760s	37.242us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.750s	111.001us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.640s	28.710us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.810s	2.019us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.660s	7.562us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.780s	47.862us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.780s	47.862us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	11.500s	14.275ms	1	1	100.00
		spi_device_tpm_sts_read	1.630s	95.157us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	23.270s	5.478ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	8.330s	4.972ms	1	1	100.00
		spi_device_flash_all	2.284m	47.114ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	10.680s	16.850ms	1	1	100.00
		spi_device_flash_all	2.284m	47.114ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	10.680s	16.850ms	1	1	100.00
		spi_device_flash_all	2.284m	47.114ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	2.284m	47.114ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	4.880s	309.504us	1	1	100.00
		spi_device_flash_all	2.284m	47.114ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	4.880s	309.504us	1	1	100.00
		spi_device_flash_all	2.284m	47.114ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	4.880s	309.504us	1	1	100.00
		spi_device_flash_all	2.284m	47.114ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	4.880s	309.504us	1	1	100.00
		spi_device_flash_all	2.284m	47.114ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	4.880s	309.504us	1	1	100.00
		spi_device_flash_all	2.284m	47.114ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	3.170s	608.434us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	8.180s	384.626us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	8.180s	384.626us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	8.180s	384.626us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	6.420s	1.468ms	1	1	100.00
		spi_device_read_buffer_direct	4.990s	6.116ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	8.180s	384.626us	1	1	100.00
		spi_device_flash_all	2.284m	47.114ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	2.284m	47.114ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	2.284m	47.114ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	4.110s	732.160us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	4.110s	732.160us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	33.030s	7.594ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	43.010s	12.389ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.960s	88.445us	1	1	100.00
V2	alert_test	spi_device_alert_test	1.750s	16.312us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.620s	16.969us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.270s	230.562us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.270s	230.562us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.020s	33.758us	1	1	100.00
		spi_device_csr_rw	2.050s	36.282us	1	1	100.00
		spi_device_csr_aliasing	15.420s	14.321ms	1	1	100.00
		spi_device_same_csr_outstanding	3.870s	191.981us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.020s	33.758us	1	1	100.00
		spi_device_csr_rw	2.050s	36.282us	1	1	100.00
		spi_device_csr_aliasing	15.420s	14.321ms	1	1	100.00
		spi_device_same_csr_outstanding	3.870s	191.981us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.950s	205.083us	1	1	100.00
		spi_device_tl_intg_err	16.120s	1.324ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	16.120s	1.324ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	20.290s	3.312ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.8205074013866521632108391792334642112268786304379436763622629921197062470455
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1152795 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[49])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1152795 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1152795 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[945])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.55439371709853707427628503064991540473943376125453943199373106249512877800292
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   5020726 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x532afc [10100110010101011111100] vs 0x0 [0])
        UVM_ERROR @   5029726 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x826cf9 [100000100110110011111001] vs 0x0 [0])
        UVM_ERROR @   5095726 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x8745ba [100001110100010110111010] vs 0x0 [0])
        UVM_ERROR @   5131726 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1b5f04 [110110101111100000100] vs 0x0 [0])
        UVM_ERROR @   5205726 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x110a71 [100010000101001110001] vs 0x0 [0])