SPI_DEVICE/2P Simulation Results

Tuesday May 27 2025 18:36:03 UTC

GitHub Revision: 872a98e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	51.250s	9.239ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.390s	50.273us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.360s	42.505us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	28.590s	10.797ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	6.120s	113.458us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.110s	352.588us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.360s	42.505us	1	1	100.00
		spi_device_csr_aliasing	6.120s	113.458us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.630s	40.562us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.230s	71.799us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.730s	56.033us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.910s	59.375us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	1.580s	46.081us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	2.610s	279.355us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.610s	279.355us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	4.400s	1.433ms	1	1	100.00
		spi_device_tpm_sts_read	1.690s	129.885us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	16.590s	2.660ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	8.650s	903.233us	1	1	100.00
		spi_device_flash_all	35.060s	7.630ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	4.190s	166.274us	1	1	100.00
		spi_device_flash_all	35.060s	7.630ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	4.190s	166.274us	1	1	100.00
		spi_device_flash_all	35.060s	7.630ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	35.060s	7.630ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	8.540s	7.147ms	1	1	100.00
		spi_device_flash_all	35.060s	7.630ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	8.540s	7.147ms	1	1	100.00
		spi_device_flash_all	35.060s	7.630ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	8.540s	7.147ms	1	1	100.00
		spi_device_flash_all	35.060s	7.630ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	8.540s	7.147ms	1	1	100.00
		spi_device_flash_all	35.060s	7.630ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	8.540s	7.147ms	1	1	100.00
		spi_device_flash_all	35.060s	7.630ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	6.250s	410.784us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	2.700s	76.784us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.700s	76.784us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.700s	76.784us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	9.630s	604.963us	1	1	100.00
		spi_device_read_buffer_direct	10.640s	876.095us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.700s	76.784us	1	1	100.00
		spi_device_flash_all	35.060s	7.630ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	35.060s	7.630ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	35.060s	7.630ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.770s	1.177ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.770s	1.177ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	51.250s	9.239ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.264m	16.164ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.970s	42.176us	1	1	100.00
V2	alert_test	spi_device_alert_test	1.800s	14.798us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.570s	54.581us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.960s	322.612us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.960s	322.612us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.390s	50.273us	1	1	100.00
		spi_device_csr_rw	2.360s	42.505us	1	1	100.00
		spi_device_csr_aliasing	6.120s	113.458us	1	1	100.00
		spi_device_same_csr_outstanding	3.310s	45.610us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.390s	50.273us	1	1	100.00
		spi_device_csr_rw	2.360s	42.505us	1	1	100.00
		spi_device_csr_aliasing	6.120s	113.458us	1	1	100.00
		spi_device_same_csr_outstanding	3.310s	45.610us	1	1	100.00
V2		TOTAL			22	22	100.00
V2S	tl_intg_err	spi_device_sec_cm	2.170s	354.045us	1	1	100.00
		spi_device_tl_intg_err	16.740s	2.203ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	16.740s	2.203ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	19.830s	11.551ms	1	1	100.00
		TOTAL			33	33	100.00