SRAM_CTRL/MAIN Simulation Results

Tuesday May 27 2025 18:36:03 UTC

GitHub Revision: 872a98e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	53.620s	5.499ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.610s	24.874us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.550s	32.758us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.540s	129.544us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.730s	57.445us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.660s	2.121ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.550s	32.758us	1	1	100.00
		sram_ctrl_csr_aliasing	1.730s	57.445us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.089m	24.614ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.150m	11.588ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	10.825m	91.381ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.294m	4.836ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	6.823m	335.291ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	2.145m	20.583ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	58.330s	20.827ms	1	1	100.00
V2	executable	sram_ctrl_executable	1.503m	15.969ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	6.270s	962.175us	1	1	100.00
		sram_ctrl_partial_access_b2b	2.764m	4.290ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	27.010s	3.050ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	1.099m	838.105us	1	1	100.00
		sram_ctrl_throughput_w_readback	13.780s	733.792us	1	1	100.00
V2	regwen	sram_ctrl_regwen	5.101m	23.477ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.550s	6.717ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	13.651m	37.188ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.840s	37.279us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.500s	269.879us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.500s	269.879us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.610s	24.874us	1	1	100.00
		sram_ctrl_csr_rw	1.550s	32.758us	1	1	100.00
		sram_ctrl_csr_aliasing	1.730s	57.445us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.700s	16.596us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.610s	24.874us	1	1	100.00
		sram_ctrl_csr_rw	1.550s	32.758us	1	1	100.00
		sram_ctrl_csr_aliasing	1.730s	57.445us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.700s	16.596us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	19.510s	7.530ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.630s	8.452us	0	1	0.00
		sram_ctrl_tl_intg_err	2.350s	364.045us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.630s	8.452us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.350s	364.045us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	5.101m	23.477ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	5.101m	23.477ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.550s	32.758us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	1.503m	15.969ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	1.503m	15.969ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	1.503m	15.969ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	58.330s	20.827ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.580s	1.345ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	19.510s	7.530ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	9.930s	2.754ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	53.620s	5.499ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	53.620s	5.499ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	1.503m	15.969ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.630s	8.452us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	58.330s	20.827ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.630s	8.452us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.630s	8.452us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	53.620s	5.499ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.630s	8.452us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	28.750s	1.140ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(!$isunknown(rdata_o))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.66225864119658096064204453000927403862411964139165876172126598100815540215172
      Line 96, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   8451679 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   8451679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---