SRAM_CTRL/RET Simulation Results

Tuesday May 27 2025 18:36:03 UTC

GitHub Revision: 872a98e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	8.020s	198.249us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.540s	103.867us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.530s	21.489us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.090s	89.306us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.620s	45.453us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.240s	93.995us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.530s	21.489us	1	1	100.00
		sram_ctrl_csr_aliasing	1.620s	45.453us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	8.830s	360.364us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.050s	803.927us	1	1	100.00
V1		TOTAL			7	8	87.50
V2	multiple_keys	sram_ctrl_multiple_keys	1.183m	1.886ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.290m	11.538ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	47.900s	3.183ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	13.201m	10.745ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	8.370s	3.558ms	1	1	100.00
V2	executable	sram_ctrl_executable	9.287m	37.458ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	18.830s	3.900ms	1	1	100.00
		sram_ctrl_partial_access_b2b	6.234m	137.614ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	54.240s	513.605us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	25.490s	131.693us	1	1	100.00
		sram_ctrl_throughput_w_readback	43.530s	239.680us	1	1	100.00
V2	regwen	sram_ctrl_regwen	4.900m	22.664ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.830s	47.562us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	18.097m	201.039ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.860s	12.996us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.790s	39.914us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.790s	39.914us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.540s	103.867us	1	1	100.00
		sram_ctrl_csr_rw	1.530s	21.489us	1	1	100.00
		sram_ctrl_csr_aliasing	1.620s	45.453us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.610s	78.918us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.540s	103.867us	1	1	100.00
		sram_ctrl_csr_rw	1.530s	21.489us	1	1	100.00
		sram_ctrl_csr_aliasing	1.620s	45.453us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.610s	78.918us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.340s	552.704us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.570s	3.042us	0	1	0.00
		sram_ctrl_tl_intg_err	2.300s	193.293us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.570s	3.042us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.300s	193.293us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	4.900m	22.664ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	4.900m	22.664ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.530s	21.489us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	9.287m	37.458ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	9.287m	37.458ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	9.287m	37.458ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	8.370s	3.558ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.040s	36.975us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.340s	552.704us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.790s	106.163us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	8.020s	198.249us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	8.020s	198.249us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	9.287m	37.458ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.570s	3.042us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	8.370s	3.558ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.570s	3.042us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.570s	3.042us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	8.020s	198.249us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.570s	3.042us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.038m	839.960us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.15697955896014029720325378843880031830215455198325272129685462009712992886781
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   3041859 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   3041859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.sram_ctrl_csr_mem_rw_with_rand_reset.111915891360672185436942208669503646643545508914123002754252064040606909346806
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  93995354 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (40 [0x28] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
        UVM_INFO @  93995354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---