SYSRST_CTRL Simulation Results

Tuesday May 27 2025 18:36:03 UTC

GitHub Revision: 872a98e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	5.660s	2.112ms	1	1	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	6.070s	2.457ms	1	1	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	5.550s	2.393ms	1	1	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	2.130s	2.401ms	1	1	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	7.970s	4.026ms	1	1	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	1.890s	2.402ms	1	1	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	9.910s	3.850ms	1	1	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	8.550s	2.701ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	2.130s	2.128ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	1.890s	2.402ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	8.550s	2.701ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	5.822m	176.278ms	1	1	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	30.670s	62.939ms	1	1	100.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	3.300s	3.377ms	1	1	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	5.240s	4.590ms	0	1	0.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	4.070s	2.516ms	1	1	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	3.590s	2.138ms	1	1	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	8.920s	3.799ms	1	1	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	2.020s	2.686ms	1	1	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	2.510s	5.141ms	1	1	100.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	18.590s	36.385ms	1	1	100.00
V2	stress_all	sysrst_ctrl_stress_all	25.760s	16.869ms	1	1	100.00
V2	alert_test	sysrst_ctrl_alert_test	2.570s	2.022ms	1	1	100.00
V2	intr_test	sysrst_ctrl_intr_test	5.570s	2.015ms	1	1	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	3.200s	2.243ms	1	1	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	3.200s	2.243ms	1	1	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	7.970s	4.026ms	1	1	100.00
		sysrst_ctrl_csr_rw	1.890s	2.402ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	8.550s	2.701ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	2.780s	4.255ms	1	1	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	7.970s	4.026ms	1	1	100.00
		sysrst_ctrl_csr_rw	1.890s	2.402ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	8.550s	2.701ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	2.780s	4.255ms	1	1	100.00
V2		TOTAL			14	15	93.33
V2S	tl_intg_err	sysrst_ctrl_sec_cm	12.230s	22.074ms	1	1	100.00
		sysrst_ctrl_tl_intg_err	1.363m	42.453ms	1	1	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	1.363m	42.453ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	10.820s	4.564ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:251) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 1 failures:
  • Test sysrst_ctrl_edge_detect has 1 failures.

    • 0.sysrst_ctrl_edge_detect.48616698081533875649952050641110213260356209105639360017480139514183952571068
      Line 389, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_edge_detect/latest/run.log

        UVM_ERROR @ 4589570065 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_ERROR @ 4589630064 ps: (cip_base_scoreboard.sv:263) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
        UVM_INFO @ 4589630064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---