UART Simulation Results

Tuesday May 27 2025 18:36:03 UTC

GitHub Revision: 872a98e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	16.870s	5.359ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.640s	19.433us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.540s	81.573us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.820s	175.106us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.910s	58.816us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.600s	58.053us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.540s	81.573us	1	1	100.00
		uart_csr_aliasing	1.910s	58.816us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	6.610s	8.473ms	1	1	100.00
V2	parity	uart_smoke	16.870s	5.359ms	1	1	100.00
		uart_tx_rx	6.610s	8.473ms	1	1	100.00
V2	parity_error	uart_intr	2.950s	5.540ms	1	1	100.00
		uart_rx_parity_err	17.780s	28.279ms	1	1	100.00
V2	watermark	uart_tx_rx	6.610s	8.473ms	1	1	100.00
		uart_intr	2.950s	5.540ms	1	1	100.00
V2	fifo_full	uart_fifo_full	13.370s	64.781ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	2.315m	107.977ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	54.340s	86.791ms	1	1	100.00
V2	rx_frame_err	uart_intr	2.950s	5.540ms	1	1	100.00
V2	rx_break_err	uart_intr	2.950s	5.540ms	1	1	100.00
V2	rx_timeout	uart_intr	2.950s	5.540ms	1	1	100.00
V2	perf	uart_perf	2.953m	12.026ms	1	1	100.00
V2	sys_loopback	uart_loopback	14.730s	9.432ms	1	1	100.00
V2	line_loopback	uart_loopback	14.730s	9.432ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	1.022m	57.619ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	3.940s	1.615ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.930s	851.232us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	11.230s	6.803ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	2.981m	242.699ms	1	1	100.00
V2	stress_all	uart_stress_all	27.225m	53.481ms	1	1	100.00
V2	alert_test	uart_alert_test	1.460s	12.280us	1	1	100.00
V2	intr_test	uart_intr_test	1.590s	44.358us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.220s	31.416us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.220s	31.416us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.640s	19.433us	1	1	100.00
		uart_csr_rw	1.540s	81.573us	1	1	100.00
		uart_csr_aliasing	1.910s	58.816us	1	1	100.00
		uart_same_csr_outstanding	1.610s	17.843us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.640s	19.433us	1	1	100.00
		uart_csr_rw	1.540s	81.573us	1	1	100.00
		uart_csr_aliasing	1.910s	58.816us	1	1	100.00
		uart_same_csr_outstanding	1.610s	17.843us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	2.130s	60.303us	1	1	100.00
		uart_tl_intg_err	1.780s	54.994us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.780s	54.994us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	50.080s	25.786ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00