CHIP Simulation Results

Tuesday May 27 2025 18:36:03 UTC

GitHub Revision: `872a98e`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.097m	2.519ms	1	1	100.00
		chip_sw_example_rom	1.270m	2.757ms	1	1	100.00
		chip_sw_example_manufacturer	1.835m	2.986ms	1	1	100.00
		chip_sw_example_concurrency	2.533m	2.401ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	2.493m	4.188ms	1	1	100.00
V1	csr_rw	chip_csr_rw	5.983m	6.363ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	7.998m	8.056ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	47.443m	27.771ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	56.600s	2.472ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	47.443m	27.771ms	1	1	100.00
		chip_csr_rw	5.983m	6.363ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	7.060s	219.871us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.382m	4.375ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.382m	4.375ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.382m	4.375ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	6.691m	4.767ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	6.691m	4.767ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.746m	4.018ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.302m	4.994ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.789m	4.251ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	5.887m	4.773ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	28.148m	13.312ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	3.855m	4.128ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.402m	5.954ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.402m	5.954ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.332m	2.751ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.956m	5.621ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	3.086m	3.935ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	16.241m	14.951ms	1	1	100.00
		chip_tap_straps_testunlock0	6.138m	7.163ms	1	1	100.00
		chip_tap_straps_rma	5.575m	6.016ms	1	1	100.00
		chip_tap_straps_prod	21.886m	18.781ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.419m	3.057ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	11.367m	8.335ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.170m	6.274ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.170m	6.274ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	8.849m	8.527ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	38.837m	23.922ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.897m	3.698ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.335m	5.173ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.298m	18.323ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.245m	3.265ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	12.195m	7.834ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.165m	2.658ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	22.157m	11.451ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.179m	2.668ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.776m	5.382ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.038m	2.893ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.293m	3.231ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	6.846m	6.883ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.206m	5.462ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.331m	3.226ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.206m	5.462ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.227m	3.100ms	1	1	100.00
		chip_sw_aes_smoketest	2.647m	2.670ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.488m	3.183ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.170m	2.921ms	1	1	100.00
		chip_sw_csrng_smoketest	2.203m	2.596ms	1	1	100.00
		chip_sw_entropy_src_smoketest	5.013m	3.557ms	1	1	100.00
		chip_sw_gpio_smoketest	2.653m	2.611ms	1	1	100.00
		chip_sw_hmac_smoketest	3.537m	3.327ms	1	1	100.00
		chip_sw_kmac_smoketest	2.249m	3.641ms	1	1	100.00
		chip_sw_otbn_smoketest	20.950m	11.561ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.974m	5.077ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	4.504m	5.453ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.251m	2.639ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.721m	2.624ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.216m	2.885ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.315m	3.078ms	1	1	100.00
		chip_sw_uart_smoketest	1.986m	3.204ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.807m	2.830ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.902m	4.333ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.053h	61.089ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	40.614m	15.096ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.880m	4.700ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.353m	2.770ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.690m	2.783ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.744h	53.338ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.957h	56.121ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	43.630s	2.270ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	43.630s	2.270ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	47.443m	27.771ms	1	1	100.00
		chip_same_csr_outstanding	44.641m	29.232ms	1	1	100.00
		chip_csr_hw_reset	2.493m	4.188ms	1	1	100.00
		chip_csr_rw	5.983m	6.363ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	47.443m	27.771ms	1	1	100.00
		chip_same_csr_outstanding	44.641m	29.232ms	1	1	100.00
		chip_csr_hw_reset	2.493m	4.188ms	1	1	100.00
		chip_csr_rw	5.983m	6.363ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	29.870s	606.728us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	5.040s	53.825us	1	1	100.00
		xbar_smoke_large_delays	56.410s	8.972ms	1	1	100.00
		xbar_smoke_slow_rsp	28.920s	3.292ms	1	1	100.00
		xbar_random_zero_delays	21.420s	436.951us	1	1	100.00
		xbar_random_large_delays	1.700m	17.812ms	1	1	100.00
		xbar_random_slow_rsp	2.883m	20.417ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	14.770s	559.114us	1	1	100.00
		xbar_error_and_unmapped_addr	15.010s	591.847us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	6.090s	158.065us	1	1	100.00
		xbar_error_and_unmapped_addr	15.010s	591.847us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	1.171m	3.260ms	1	1	100.00
		xbar_access_same_device_slow_rsp	1.610m	11.189ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	42.130s	2.094ms	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	1.213m	1.940ms	1	1	100.00
		xbar_stress_all_with_error	2.028m	6.051ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	7.660m	16.622ms	1	1	100.00
		xbar_stress_all_with_reset_error	55.800s	231.750us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	40.614m	15.096ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	33.685m	26.311ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	41.078m	15.046ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	31.689m	11.175ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	42.086m	15.628ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	40.886m	16.316ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	41.510m	15.617ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	37.617m	14.170ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	27.330s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	27.450s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	27.170s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	27.830s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	31.450s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	35.060s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	27.150s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	27.230s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	27.330s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	26.300s	10.300us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	26.610s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	26.130s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	26.620s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	26.370s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	26.430s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	25.880s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	25.890s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	26.510s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	26.160s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	26.710s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	27.710s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	26.570s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	26.770s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	27.460s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	30.370s	10.320us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	29.096m	11.317ms	1	1	100.00
		rom_e2e_asm_init_dev	38.378m	14.984ms	1	1	100.00
		rom_e2e_asm_init_prod	38.425m	15.487ms	1	1	100.00
		rom_e2e_asm_init_prod_end	37.991m	15.041ms	1	1	100.00
		rom_e2e_asm_init_rma	34.619m	15.097ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	36.064m	15.336ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	36.287m	15.078ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	37.275m	15.755ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	38.529m	15.495ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	48.795m	35.287ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	48.795m	35.287ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.638m	3.374ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.245m	3.265ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.091m	2.842ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.163m	3.101ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	12.395m	6.949ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.046m	2.979ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	4.117m	4.063ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	5.993m	4.872ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	8.097m	5.571ms	1	1	100.00
		chip_plic_all_irqs_10	5.101m	4.174ms	1	1	100.00
		chip_plic_all_irqs_20	5.898m	4.078ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	3.475m	3.812ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	16.887m	13.383ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.900m	3.353ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	3.061m	3.263ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	10.073m	11.011ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	14.677m	7.487ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	16.024m	7.694ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	12.845m	7.903ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	1.948h	254.502ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.113m	4.210ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	3.974m	5.077ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.113m	4.210ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	9.299m	10.915ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	9.299m	10.915ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.439m	6.231ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	6.090m	5.399ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.400m	6.368ms	1	1	100.00
		chip_sw_aes_idle	2.163m	3.101ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.702m	3.431ms	1	1	100.00
		chip_sw_kmac_idle	2.100m	2.313ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	4.484m	3.917ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	3.228m	4.771ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	3.381m	3.967ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	4.243m	4.442ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	12.200m	9.849ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.108m	3.397ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.927m	4.803ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.578m	4.082ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.055m	5.084ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.626m	3.667ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.452m	4.953ms	1	1	100.00
		chip_sw_ast_clk_outputs	8.849m	8.527ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	10.725m	10.410ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.578m	4.082ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.055m	5.084ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.897m	3.698ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.335m	5.173ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.298m	18.323ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.245m	3.265ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	12.195m	7.834ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.165m	2.658ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	22.157m	11.451ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.179m	2.668ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.776m	5.382ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.038m	2.893ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.014m	2.507ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	5.520m	4.784ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	10.308m	7.123ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	49.930m	24.363ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.647m	2.664ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.879m	3.764ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	19.210m	12.596ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	3.019m	3.484ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	4.665m	4.919ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	17.527m	22.437ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	2.014h	94.324ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	8.849m	8.527ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.357m	4.652ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.136m	3.018ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	5.993m	4.872ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	14.677m	7.487ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	11.600m	6.165ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	3.120m	2.783ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	5.670m	6.285ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.419m	3.244ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	54.633m	20.280ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.397m	2.736ms	1	1	100.00
		chip_sw_edn_entropy_reqs	8.887m	6.398ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.397m	2.736ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	11.600m	6.165ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.372m	2.578ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	17.057m	18.355ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	10.141m	5.986ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.335m	5.173ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.951m	4.210ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.897m	3.698ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	59.467m	43.574ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	17.057m	18.355ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.575m	3.612ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	9.645m	6.223ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.877m	3.607ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	59.467m	43.574ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.877m	3.607ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.877m	3.607ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	3.877m	3.607ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.877m	3.607ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	5.993m	4.872ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	5.704m	14.899ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	7.859m	4.988ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	6.096m	5.569ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	6.096m	5.569ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.247m	3.275ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.165m	2.658ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.702m	3.431ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.738m	2.836ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	5.867m	4.074ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	7.170m	4.768ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	6.129m	5.245ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	5.157m	3.944ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	5.054m	4.469ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	9.645m	6.223ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	22.157m	11.451ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	13.730m	8.403ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	12.395m	6.949ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	42.144m	15.407ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.630m	2.972ms	1	1	100.00
		chip_sw_kmac_mode_kmac	3.031m	2.877ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.179m	2.668ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	9.645m	6.223ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	5.008m	5.160ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.121m	2.831ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	19.291m	9.287ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.100m	2.313ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	4.117m	4.063ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	16.241m	14.951ms	1	1	100.00
		chip_tap_straps_rma	5.575m	6.016ms	1	1	100.00
		chip_tap_straps_prod	21.886m	18.781ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	1.974m	2.618ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	5.008m	5.160ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	5.008m	5.160ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	5.008m	5.160ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	13.847m	8.405ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	3.877m	3.607ms	1	1	100.00
		chip_sw_flash_rma_unlocked	59.467m	43.574ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.643m	3.356ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	9.249m	6.438ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	6.282m	6.104ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.414m	7.197ms	1	1	100.00
		chip_sw_lc_ctrl_transition	5.008m	5.160ms	1	1	100.00
		chip_sw_keymgr_key_derivation	9.645m	6.223ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	4.743m	9.337ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	9.560m	10.199ms	1	1	100.00
		chip_prim_tl_access	5.704m	14.899ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	10.725m	10.410ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.108m	3.397ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.927m	4.803ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.578m	4.082ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.055m	5.084ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.626m	3.667ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.452m	4.953ms	1	1	100.00
		chip_tap_straps_dev	16.241m	14.951ms	1	1	100.00
		chip_tap_straps_rma	5.575m	6.016ms	1	1	100.00
		chip_tap_straps_prod	21.886m	18.781ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.447m	7.608ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.070m	3.114ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.348m	2.922ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.409m	3.274ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1.528m	3.305ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	23.930m	35.832ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.447m	7.608ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.008h	50.691ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.048h	51.302ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	7.568m	9.580ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.006h	48.170ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	23.930m	35.832ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.064m	2.983ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.036m	2.138ms	1	1	100.00
		rom_volatile_raw_unlock	1.278m	2.585ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	54.134m	17.048ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.298m	18.323ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.400m	6.368ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.400m	6.368ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.400m	6.368ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.725m	3.490ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	5.008m	5.160ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	17.057m	18.355ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.725m	3.490ms	1	1	100.00
		chip_sw_keymgr_key_derivation	9.645m	6.223ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.267m	5.263ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.227m	3.006ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	17.057m	18.355ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.725m	3.490ms	1	1	100.00
		chip_sw_keymgr_key_derivation	9.645m	6.223ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.267m	5.263ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.227m	3.006ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	5.008m	5.160ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	4.716m	4.732ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	1.974m	2.618ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.643m	3.356ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	9.249m	6.438ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	6.282m	6.104ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.414m	7.197ms	1	1	100.00
		chip_sw_lc_ctrl_transition	5.008m	5.160ms	1	1	100.00
		chip_prim_tl_access	5.704m	14.899ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	5.704m	14.899ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	17.722m	7.916ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	5.102m	8.276ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	16.942m	25.525ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	3.975m	7.110ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	6.746m	10.296ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	5.007m	5.823ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	12.917m	24.384ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	15.364m	17.648ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	9.299m	10.915ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	13.404m	12.239ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	5.063m	4.621ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	5.102m	8.276ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.706m	4.582ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	31.495m	32.307ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	3.921m	5.375ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	3.968m	5.674ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	22.126m	25.954ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	8.038m	5.828ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	15.927m	9.356ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	28.564m	27.890ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	1.919m	2.507ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	5.993m	4.872ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	4.743m	9.337ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	4.743m	9.337ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	15.927m	9.356ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	22.126m	25.954ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	5.063m	4.621ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.974m	5.077ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.191m	4.061ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	4.127m	3.921ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	3.693m	4.415ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	16.887m	13.383ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	1.738m	2.099ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	5.993m	4.872ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	16.024m	7.694ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.308m	4.667ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.696m	4.642ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.568m	2.999ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.227m	3.006ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	4.127m	3.921ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	4.127m	3.921ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.669m	4.983ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	13.695m	13.938ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.191m	4.061ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	5.122m	4.543ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	3.893m	6.455ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	5.575m	6.016ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	3.447m	7.608ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	8.097m	5.571ms	1	1	100.00
		chip_plic_all_irqs_10	5.101m	4.174ms	1	1	100.00
		chip_plic_all_irqs_20	5.898m	4.078ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.147m	2.871ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	3.417m	3.306ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	40.614m	15.096ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	6.907m	7.139ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.595m	3.579ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.138m	3.548ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	3.115m	3.385ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	6.267m	5.263ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.776m	5.382ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	5.124m	5.979ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	6.057m	6.618ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	9.560m	10.199ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	5.993m	4.872ms	1	1	100.00
		chip_sw_data_integrity_escalation	6.170m	6.274ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	8.038m	5.828ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	18.399m	23.127ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	3.206m	3.614ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.137m	3.345ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.190m	5.000ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	18.399m	23.127ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	18.399m	23.127ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	35.521m	20.538ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	35.521m	20.538ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.011m	6.547ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	48.795m	35.287ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.157m	2.766ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.779m	2.662ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.308m	3.410ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	4.457m	3.179ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	16.000m	7.842ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.286h	31.368ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	29.528m	12.574ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	3.042m	3.198ms	1	1	100.00
V2		TOTAL			240	275	87.27
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	3.314m	3.235ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.915m	2.286ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.458h	71.705ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	14.191m	5.933ms	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	17.073m	11.884ms	1	1	100.00
		rom_e2e_jtag_debug_dev	17.609m	11.951ms	1	1	100.00
		rom_e2e_jtag_debug_rma	16.854m	11.957ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.913m	3.950ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.001m	3.933ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.160m	4.201ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	11.200s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	7.438m	5.208ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	5.048m	2.995ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	13.035m	5.918ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	14.566m	6.719ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.571m	2.758ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	8.186m	4.912ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.270m	1.823ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	4.168m	4.526ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.990m	5.766ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.858m	4.287ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	15.927m	9.356ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	17.073m	11.884ms	1	1	100.00
		rom_e2e_jtag_debug_dev	17.609m	11.951ms	1	1	100.00
		rom_e2e_jtag_debug_rma	16.854m	11.957ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	5.667m	4.779ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	5.993m	4.872ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.379h	38.327ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.379h	38.327ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	3.274m	3.987ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	6.691m	4.767ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	47.011m	18.856ms	1	1	100.00
V3		TOTAL			22	23	95.65
	Unmapped tests	chip_sival_flash_info_access	2.525m	3.131ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	6.590m	6.123ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.333m	2.645ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.513m	3.246ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.755m	4.589ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	16.267s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	3.252m	3.218ms	1	1	100.00
		TOTAL			286	325	88.00

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.11562955980985016253578272314629175184717458468521128655862382341264637831411
    Line 695, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.79512915626206352470743751268135017172031128581428441317931171203724024317359
    Line 736, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.45449029744760706025945893021424064793452972908419095880232633961436281187884
    Line 667, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.71536987408787886205067232892417901303314016487069229361246388656640022482283
    Line 672, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.40713648627667333043656625875039488687397200569294735414464873146392596978472
    Line 748, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.11201350934273028173035762589453854137620248826023740595947887119058406867311
    Line 744, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.79239100416444612544018768165075075832920996076025847545112155524987421812181
    Line 717, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.15639703793471204926553073288683623531375954506304040786883777669552570736038
    Line 646, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.17361290860954434173443189882122275669480027830314221959323167155807630631473
    Line 692, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.104528009576113975015846374141483417752974541432486612082013664986840073710826
    Line 682, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.100283603895336300649800691777971740716972565397850489449709505912920302407384
    Line 703, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.113129377584040083156177287375681660800010678959889301389426763093745954334487
    Line 720, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.90690746910838135484953913272849763251083360523287730927225374658005484055715
    Line 699, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.58937317834055139799715448497413661035904631819705105445907624251293215646268
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.168s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.76591557229665459631728757354575362512699496598540634690505213702510392352640
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.142s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.50926297609700174972060954133013076957626461992321052203184721741938872711364
    Line 909, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.99480849434276457095198679617056073860736411110841812822156421797146932352643
    Line 670, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.63128129657703707355194871376508335011939233055004003350590966126099614816512
    Line 850, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.93275513500277650724490890484001138254200692317605211903268298085100837592667
    Line 654, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.12397950161857387268406783760879358394276840024088703818767176244864556026723
    Line 471, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3578.874280 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3578.874280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@105229) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.318270306703786906050099454019145779188961327534890023612767750253752681021
Line 473, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 3921.205968 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@105229) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3921.205968 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.77355953845134336905400589927754065243833628213462121605232559200869437534295
    Line 429, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 35287.169240 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 35287.169240 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.6650261321433146687151662512892235941173917859448252199309472615394260972951
    Line 423, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2979.391722 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 2979.391722 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.24662774184820838367932975953865429170717181048384453441238825326694595391580
    Line 405, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3263.051756 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 3263.051756 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:587) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.90096255392356311933106832080514079497459854933775105742263699263978626371707
    Line 407, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 2783.186566 us: (cip_base_vseq.sv:587) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 2783.186566 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36895) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.21305724830041341126504677136355925366056060576583766168042415298179078487159
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2269.796722 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36895) { a_addr: 'h107c8  a_data: 'hbc666c5e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h33  a_opcode: 'h4  a_user: 'h19526  d_param: 'h0  d_source: 'h33  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2269.796722 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.112885632875323351527263199195534497045245548903928356433156011792886600612689
    Line 421, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2285.620988 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2285.620988 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.7805548484592951271912946159468180887244333900376687898932171280875794935334
    Line 409, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 2769.688000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2769.688000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.105077658061348477854235476699777496186028190216548391495851642078754587181709
    Line 425, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 2783.020500 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2783.020500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.98150975623870037998964700774242614109131253124482243258053664032039523058133
    Line 440, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 23922.401776 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 23922.401776 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.27373455434967886154109089393161015026617866878278278959557643264722390565045
    Line 700, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.51106126146858736202574098340674788543252536692037404505714720774753991088453
    Line 708, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32085) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.69966582391968667452774331324238830400886390219007715159113338151138522589351
Line 226, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2471.508520 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32085) { a_addr: 'h106b4  a_data: 'h8c034083  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h7  a_opcode: 'h4  a_user: 'h19ec7  d_param: 'h0  d_source: 'h7  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2471.508520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---