ADC_CTRL Simulation Results

Wednesday May 28 2025 18:36:19 UTC

GitHub Revision: 645424b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	17.230s	6.033ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.120s	649.609us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.530s	560.356us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	12.870s	22.785ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.520s	721.466us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.240s	438.883us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.530s	560.356us	1	1	100.00
		adc_ctrl_csr_aliasing	2.520s	721.466us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	56.440s	320.648ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	7.514m	497.080ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	10.968m	496.455ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	2.009m	321.741ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	43.080s	181.343ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	2.619m	203.861ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	2.150m	167.114ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	2.139m	326.797ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	7.250s	3.530ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	47.030s	26.275ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	1.135m	127.228ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	6.386m	445.314ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	2.090s	431.196us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.930s	360.746us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.470s	636.197us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.470s	636.197us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.120s	649.609us	1	1	100.00
		adc_ctrl_csr_rw	2.530s	560.356us	1	1	100.00
		adc_ctrl_csr_aliasing	2.520s	721.466us	1	1	100.00
		adc_ctrl_same_csr_outstanding	3.730s	2.627ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.120s	649.609us	1	1	100.00
		adc_ctrl_csr_rw	2.530s	560.356us	1	1	100.00
		adc_ctrl_csr_aliasing	2.520s	721.466us	1	1	100.00
		adc_ctrl_same_csr_outstanding	3.730s	2.627ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	10.890s	3.946ms	1	1	100.00
		adc_ctrl_tl_intg_err	6.410s	4.604ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	6.410s	4.604ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	10.980s	17.984ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00