AES/MASKED Simulation Results

Wednesday May 28 2025 18:36:19 UTC

GitHub Revision: 645424b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	68.231us	1	1	100.00
V1	smoke	aes_smoke	5.000s	69.961us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	93.861us	1	1	100.00
V1	csr_rw	aes_csr_rw	5.000s	87.095us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	12.000s	3.335ms	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	89.336us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	99.398us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	87.095us	1	1	100.00
		aes_csr_aliasing	5.000s	89.336us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	algorithm	aes_smoke	5.000s	69.961us	1	1	100.00
		aes_config_error	6.000s	244.069us	1	1	100.00
		aes_stress	5.000s	182.709us	1	1	100.00
V2	key_length	aes_smoke	5.000s	69.961us	1	1	100.00
		aes_config_error	6.000s	244.069us	1	1	100.00
		aes_stress	5.000s	182.709us	1	1	100.00
V2	back2back	aes_stress	5.000s	182.709us	1	1	100.00
		aes_b2b	12.000s	204.524us	1	1	100.00
V2	backpressure	aes_stress	5.000s	182.709us	1	1	100.00
V2	multi_message	aes_smoke	5.000s	69.961us	1	1	100.00
		aes_config_error	6.000s	244.069us	1	1	100.00
		aes_stress	5.000s	182.709us	1	1	100.00
		aes_alert_reset	19.000s	1.425ms	1	1	100.00
V2	failure_test	aes_man_cfg_err	5.000s	111.074us	1	1	100.00
		aes_config_error	6.000s	244.069us	1	1	100.00
		aes_alert_reset	19.000s	1.425ms	1	1	100.00
V2	trigger_clear_test	aes_clear	5.000s	205.636us	1	1	100.00
V2	nist_test_vectors	aes_nist_vectors	15.000s	900.251us	1	1	100.00
V2	reset_recovery	aes_alert_reset	19.000s	1.425ms	1	1	100.00
V2	stress	aes_stress	5.000s	182.709us	1	1	100.00
V2	sideload	aes_stress	5.000s	182.709us	1	1	100.00
		aes_sideload	6.000s	60.033us	1	1	100.00
V2	deinitialization	aes_deinit	7.000s	274.654us	1	1	100.00
V2	stress_all	aes_stress_all	15.000s	1.814ms	1	1	100.00
V2	alert_test	aes_alert_test	4.000s	69.511us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	5.000s	176.470us	1	1	100.00
V2	tl_d_illegal_access	aes_tl_errors	5.000s	176.470us	1	1	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	93.861us	1	1	100.00
		aes_csr_rw	5.000s	87.095us	1	1	100.00
		aes_csr_aliasing	5.000s	89.336us	1	1	100.00
		aes_same_csr_outstanding	5.000s	119.556us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	93.861us	1	1	100.00
		aes_csr_rw	5.000s	87.095us	1	1	100.00
		aes_csr_aliasing	5.000s	89.336us	1	1	100.00
		aes_same_csr_outstanding	5.000s	119.556us	1	1	100.00
V2		TOTAL			13	13	100.00
V2S	reseeding	aes_reseed	7.000s	283.364us	1	1	100.00
V2S	fault_inject	aes_fi	6.000s	322.860us	1	1	100.00
		aes_control_fi	5.000s	113.088us	1	1	100.00
		aes_cipher_fi	5.000s	101.982us	1	1	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	5.000s	167.227us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	5.000s	167.227us	1	1	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	5.000s	167.227us	1	1	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	5.000s	167.227us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	138.299us	1	1	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	3.178ms	1	1	100.00
		aes_tl_intg_err	6.000s	330.667us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	330.667us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	19.000s	1.425ms	1	1	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	5.000s	167.227us	1	1	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	5.000s	69.961us	1	1	100.00
		aes_stress	5.000s	182.709us	1	1	100.00
		aes_alert_reset	19.000s	1.425ms	1	1	100.00
		aes_core_fi	5.000s	97.263us	1	1	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	5.000s	167.227us	1	1	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	5.000s	63.776us	1	1	100.00
		aes_stress	5.000s	182.709us	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	5.000s	182.709us	1	1	100.00
		aes_sideload	6.000s	60.033us	1	1	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	5.000s	63.776us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	5.000s	63.776us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	5.000s	63.776us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	5.000s	63.776us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	5.000s	63.776us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	5.000s	182.709us	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	5.000s	182.709us	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	6.000s	322.860us	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	6.000s	322.860us	1	1	100.00
		aes_control_fi	5.000s	113.088us	1	1	100.00
		aes_cipher_fi	5.000s	101.982us	1	1	100.00
		aes_ctr_fi	4.000s	86.855us	1	1	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	6.000s	322.860us	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	6.000s	322.860us	1	1	100.00
		aes_control_fi	5.000s	113.088us	1	1	100.00
		aes_cipher_fi	5.000s	101.982us	1	1	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	5.000s	101.982us	1	1	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	6.000s	322.860us	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	6.000s	322.860us	1	1	100.00
		aes_control_fi	5.000s	113.088us	1	1	100.00
		aes_ctr_fi	4.000s	86.855us	1	1	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	6.000s	322.860us	1	1	100.00
		aes_control_fi	5.000s	113.088us	1	1	100.00
		aes_cipher_fi	5.000s	101.982us	1	1	100.00
		aes_ctr_fi	4.000s	86.855us	1	1	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	19.000s	1.425ms	1	1	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	6.000s	322.860us	1	1	100.00
		aes_control_fi	5.000s	113.088us	1	1	100.00
		aes_cipher_fi	5.000s	101.982us	1	1	100.00
		aes_ctr_fi	4.000s	86.855us	1	1	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	6.000s	322.860us	1	1	100.00
		aes_control_fi	5.000s	113.088us	1	1	100.00
		aes_cipher_fi	5.000s	101.982us	1	1	100.00
		aes_ctr_fi	4.000s	86.855us	1	1	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	6.000s	322.860us	1	1	100.00
		aes_control_fi	5.000s	113.088us	1	1	100.00
		aes_ctr_fi	4.000s	86.855us	1	1	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	6.000s	322.860us	1	1	100.00
		aes_control_fi	5.000s	113.088us	1	1	100.00
		aes_cipher_fi	5.000s	101.982us	1	1	100.00
V2S		TOTAL			11	11	100.00
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	6.000s	33.094us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			31	32	96.88

Failure Buckets

• UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.63844646971552990231570799223563217466781074010290377238267026372825108283992
      Line 171, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  33094287 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
        UVM_INFO @  33094287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---