EDN Simulation Results

Wednesday May 28 2025 18:36:19 UTC

GitHub Revision: 645424b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 2.120s 26.237us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.740s 125.220us 1 1 100.00
V1 csr_rw edn_csr_rw 2.010s 46.981us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 3.250s 218.390us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.930s 19.266us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.240s 93.005us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 2.010s 46.981us 1 1 100.00
edn_csr_aliasing 1.930s 19.266us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 1.880s 57.994us 1 1 100.00
V2 csrng_commands edn_genbits 1.880s 57.994us 1 1 100.00
V2 genbits edn_genbits 1.880s 57.994us 1 1 100.00
V2 interrupts edn_intr 1.830s 21.717us 1 1 100.00
V2 alerts edn_alert 1.950s 47.938us 1 1 100.00
V2 errs edn_err 2.000s 57.930us 1 1 100.00
V2 disable edn_disable 1.660s 24.244us 1 1 100.00
edn_disable_auto_req_mode 1.920s 40.481us 1 1 100.00
V2 stress_all edn_stress_all 3.730s 167.862us 1 1 100.00
V2 intr_test edn_intr_test 1.900s 11.918us 1 1 100.00
V2 alert_test edn_alert_test 1.550s 31.565us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 2.350s 42.278us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 2.350s 42.278us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.740s 125.220us 1 1 100.00
edn_csr_rw 2.010s 46.981us 1 1 100.00
edn_csr_aliasing 1.930s 19.266us 1 1 100.00
edn_same_csr_outstanding 1.730s 19.746us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.740s 125.220us 1 1 100.00
edn_csr_rw 2.010s 46.981us 1 1 100.00
edn_csr_aliasing 1.930s 19.266us 1 1 100.00
edn_same_csr_outstanding 1.730s 19.746us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 6.770s 1.669ms 1 1 100.00
edn_tl_intg_err 2.600s 126.118us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 1.730s 25.267us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 1.950s 47.938us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 6.770s 1.669ms 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 6.770s 1.669ms 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 6.770s 1.669ms 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 6.770s 1.669ms 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.950s 47.938us 1 1 100.00
edn_sec_cm 6.770s 1.669ms 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.950s 47.938us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.600s 126.118us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets