HMAC Simulation Results

Wednesday May 28 2025 18:36:19 UTC

GitHub Revision: 645424b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 11.600s 947.244us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.910s 121.763us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.750s 43.801us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 10.340s 311.568us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 3.360s 814.548us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 3.080s 75.092us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.750s 43.801us 1 1 100.00
hmac_csr_aliasing 3.360s 814.548us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 5.300s 1.112ms 1 1 100.00
V2 back_pressure hmac_back_pressure 42.180s 3.853ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.920s 197.388us 1 1 100.00
hmac_test_sha384_vectors 19.460s 215.432us 1 1 100.00
hmac_test_sha512_vectors 5.066m 18.491ms 1 1 100.00
hmac_test_hmac256_vectors 9.600s 2.660ms 1 1 100.00
hmac_test_hmac384_vectors 9.650s 1.387ms 1 1 100.00
hmac_test_hmac512_vectors 7.820s 222.403us 1 1 100.00
V2 burst_wr hmac_burst_wr 22.010s 2.556ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 2.837m 5.190ms 1 1 100.00
V2 error hmac_error 1.056m 1.777ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.212m 4.547ms 1 1 100.00
V2 save_and_restore hmac_smoke 11.600s 947.244us 1 1 100.00
hmac_long_msg 5.300s 1.112ms 1 1 100.00
hmac_back_pressure 42.180s 3.853ms 1 1 100.00
hmac_datapath_stress 2.837m 5.190ms 1 1 100.00
hmac_burst_wr 22.010s 2.556ms 1 1 100.00
hmac_stress_all 8.006m 16.979ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 11.600s 947.244us 1 1 100.00
hmac_long_msg 5.300s 1.112ms 1 1 100.00
hmac_back_pressure 42.180s 3.853ms 1 1 100.00
hmac_datapath_stress 2.837m 5.190ms 1 1 100.00
hmac_wipe_secret 1.212m 4.547ms 1 1 100.00
hmac_test_sha256_vectors 8.920s 197.388us 1 1 100.00
hmac_test_sha384_vectors 19.460s 215.432us 1 1 100.00
hmac_test_sha512_vectors 5.066m 18.491ms 1 1 100.00
hmac_test_hmac256_vectors 9.600s 2.660ms 1 1 100.00
hmac_test_hmac384_vectors 9.650s 1.387ms 1 1 100.00
hmac_test_hmac512_vectors 7.820s 222.403us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 11.600s 947.244us 1 1 100.00
hmac_long_msg 5.300s 1.112ms 1 1 100.00
hmac_back_pressure 42.180s 3.853ms 1 1 100.00
hmac_datapath_stress 2.837m 5.190ms 1 1 100.00
hmac_burst_wr 22.010s 2.556ms 1 1 100.00
hmac_error 1.056m 1.777ms 1 1 100.00
hmac_wipe_secret 1.212m 4.547ms 1 1 100.00
hmac_test_sha256_vectors 8.920s 197.388us 1 1 100.00
hmac_test_sha384_vectors 19.460s 215.432us 1 1 100.00
hmac_test_sha512_vectors 5.066m 18.491ms 1 1 100.00
hmac_test_hmac256_vectors 9.600s 2.660ms 1 1 100.00
hmac_test_hmac384_vectors 9.650s 1.387ms 1 1 100.00
hmac_test_hmac512_vectors 7.820s 222.403us 1 1 100.00
hmac_stress_all 8.006m 16.979ms 1 1 100.00
V2 stress_all hmac_stress_all 8.006m 16.979ms 1 1 100.00
V2 alert_test hmac_alert_test 1.470s 69.231us 1 1 100.00
V2 intr_test hmac_intr_test 1.500s 112.807us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.520s 210.677us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.520s 210.677us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.910s 121.763us 1 1 100.00
hmac_csr_rw 1.750s 43.801us 1 1 100.00
hmac_csr_aliasing 3.360s 814.548us 1 1 100.00
hmac_same_csr_outstanding 2.380s 288.545us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.910s 121.763us 1 1 100.00
hmac_csr_rw 1.750s 43.801us 1 1 100.00
hmac_csr_aliasing 3.360s 814.548us 1 1 100.00
hmac_same_csr_outstanding 2.380s 288.545us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.740s 235.390us 1 1 100.00
hmac_tl_intg_err 2.390s 128.786us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.390s 128.786us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 11.600s 947.244us 1 1 100.00
V3 stress_reset hmac_stress_reset 6.010s 235.616us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 58.990s 18.483ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.470s 1.761ms 1 1 100.00
TOTAL 28 28 100.00