I2C Simulation Results

Wednesday May 28 2025 18:36:19 UTC

GitHub Revision: 645424b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	25.250s	20.834ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	8.460s	830.612us	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.690s	34.209us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.840s	17.622us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.930s	2.165ms	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.110s	293.717us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.670s	105.323us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.840s	17.622us	1	1	100.00
		i2c_csr_aliasing	2.110s	293.717us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	8.770s	881.438us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	1.140m	14.404ms	1	1	100.00
V2	host_maxperf	i2c_host_perf	2.741m	48.667ms	1	1	100.00
V2	host_override	i2c_host_override	1.790s	29.269us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	2.759m	16.557ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	59.620s	2.744ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.170s	296.803us	1	1	100.00
		i2c_host_fifo_fmt_empty	5.320s	790.139us	1	1	100.00
		i2c_host_fifo_reset_rx	7.360s	572.275us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	48.480s	5.154ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	9.890s	1.160ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.620s	168.522us	1	1	100.00
V2	target_glitch	i2c_target_glitch	10.170s	32.829ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	3.746m	74.894ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	5.260s	1.718ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	43.730s	1.296ms	1	1	100.00
		i2c_target_intr_smoke	4.950s	697.987us	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.160s	635.034us	1	1	100.00
		i2c_target_fifo_reset_tx	1.840s	179.552us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	36.920s	64.333ms	1	1	100.00
		i2c_target_stress_rd	43.730s	1.296ms	1	1	100.00
		i2c_target_intr_stress_wr	30.710s	10.180ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	6.120s	11.865ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	2.160s	576.629us	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.850s	840.092us	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	3.710s	711.732us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	3.400s	495.024us	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.970s	160.124us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	2.741m	48.667ms	1	1	100.00
		i2c_host_perf_precise	2.350s	250.886us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	9.890s	1.160ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.630s	90.653us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.870s	627.452us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.840s	516.430us	1	1	100.00
		i2c_target_nack_txstretch	2.010s	476.029us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	22.050s	3.401ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.800s	602.323us	1	1	100.00
V2	alert_test	i2c_alert_test	1.390s	34.782us	1	1	100.00
V2	intr_test	i2c_intr_test	1.760s	18.514us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.890s	207.946us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.890s	207.946us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.690s	34.209us	1	1	100.00
		i2c_csr_rw	1.840s	17.622us	1	1	100.00
		i2c_csr_aliasing	2.110s	293.717us	1	1	100.00
		i2c_same_csr_outstanding	1.990s	241.695us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.690s	34.209us	1	1	100.00
		i2c_csr_rw	1.840s	17.622us	1	1	100.00
		i2c_csr_aliasing	2.110s	293.717us	1	1	100.00
		i2c_same_csr_outstanding	1.990s	241.695us	1	1	100.00
V2		TOTAL			38	38	100.00
V2S	tl_intg_err	i2c_tl_intg_err	2.480s	69.672us	1	1	100.00
		i2c_sec_cm	1.760s	74.893us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.480s	69.672us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	14.210s	351.100us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.110s	102.881us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	8.930s	1.611ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			47	50	94.00

Failure Buckets

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.92867437053864390996962053939963489787936047574436537564061594635317112866788
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 102881293 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 195 [0xc3])
        UVM_INFO @ 102881293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.21817439829572699008086849171094325179809470966733305217463057088950848051870
      Line 83, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 351100326 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 351100326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:832) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.108380646316692406422696054687170533621959657704192928054706403431362360188158
      Line 81, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1611384850 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 1611384850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---