KEYMGR Simulation Results

Wednesday May 28 2025 18:36:19 UTC

GitHub Revision: 645424b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	4.610s	219.466us	1	1	100.00
V1	random	keymgr_random	3.860s	816.637us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.610s	20.776us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.880s	25.761us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	3.800s	1.191ms	0	1	0.00
V1	csr_aliasing	keymgr_csr_aliasing	6.360s	485.205us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.250s	252.602us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.880s	25.761us	1	1	100.00
		keymgr_csr_aliasing	6.360s	485.205us	1	1	100.00
V1		TOTAL			6	7	85.71
V2	cfgen_during_op	keymgr_cfg_regwen	28.650s	859.748us	1	1	100.00
V2	sideload	keymgr_sideload	3.750s	108.057us	1	1	100.00
		keymgr_sideload_kmac	2.860s	26.493us	1	1	100.00
		keymgr_sideload_aes	4.130s	219.542us	1	1	100.00
		keymgr_sideload_otbn	3.810s	380.182us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	3.900s	94.613us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	3.970s	97.365us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	4.880s	358.902us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	5.200s	646.211us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	3.830s	279.576us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	3.550s	448.398us	1	1	100.00
V2	stress_all	keymgr_stress_all	5.220s	232.963us	0	1	0.00
V2	intr_test	keymgr_intr_test	1.870s	11.056us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.960s	26.133us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.600s	52.649us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.600s	52.649us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.610s	20.776us	1	1	100.00
		keymgr_csr_rw	1.880s	25.761us	1	1	100.00
		keymgr_csr_aliasing	6.360s	485.205us	1	1	100.00
		keymgr_same_csr_outstanding	2.610s	44.828us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.610s	20.776us	1	1	100.00
		keymgr_csr_rw	1.880s	25.761us	1	1	100.00
		keymgr_csr_aliasing	6.360s	485.205us	1	1	100.00
		keymgr_same_csr_outstanding	2.610s	44.828us	1	1	100.00
V2		TOTAL			15	16	93.75
V2S	sec_cm_additional_check	keymgr_sec_cm	7.190s	546.073us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	7.190s	546.073us	1	1	100.00
		keymgr_tl_intg_err	3.150s	91.624us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	3.040s	67.760us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	3.040s	67.760us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	3.040s	67.760us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	3.040s	67.760us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	6.620s	1.395ms	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	7.190s	546.073us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	7.190s	546.073us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	3.150s	91.624us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	3.040s	67.760us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	28.650s	859.748us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	3.860s	816.637us	1	1	100.00
		keymgr_csr_rw	1.880s	25.761us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	3.860s	816.637us	1	1	100.00
		keymgr_csr_rw	1.880s	25.761us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	3.860s	816.637us	1	1	100.00
		keymgr_csr_rw	1.880s	25.761us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	3.970s	97.365us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	3.830s	279.576us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	3.830s	279.576us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	3.860s	816.637us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	9.640s	522.593us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	7.190s	546.073us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	7.190s	546.073us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	7.190s	546.073us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	3.340s	77.166us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	3.970s	97.365us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	7.190s	546.073us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	7.190s	546.073us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	7.190s	546.073us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	3.340s	77.166us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	3.340s	77.166us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	7.190s	546.073us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	3.340s	77.166us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	7.190s	546.073us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	3.340s	77.166us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	7.890s	168.969us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			28	30	93.33

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:349) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 1 failures:

  • Test keymgr_stress_all has 1 failures.

    • 0.keymgr_stress_all.99725200316567901371481261871645070909262256478722272185582563605870121396085
      Line 1139, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 232963443 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
        UVM_INFO @ 232963443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test keymgr_csr_bit_bash has 1 failures.

    • 0.keymgr_csr_bit_bash.58076946220037831919209114521548447996219496775466033055316781709393209509534
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[10] & 'hffffffff)))'
        UVM_ERROR @ 1190963066 ps: (keymgr_csr_assert_fpv.sv:419) [ASSERT FAILED] sealing_sw_binding_5_rd_A
        UVM_INFO @ 1190963066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---