KMAC/MASKED Simulation Results

Wednesday May 28 2025 18:36:19 UTC

GitHub Revision: 645424b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.006m	19.805ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.850s	40.789us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.750s	38.758us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	14.080s	1.514ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.710s	2.085ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.210s	42.393us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.750s	38.758us	1	1	100.00
		kmac_csr_aliasing	7.710s	2.085ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.660s	37.040us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.960s	59.626us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	40.493m	85.806ms	1	1	100.00
V2	burst_write	kmac_burst_write	4.782m	7.212ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	23.354m	36.255ms	1	1	100.00
		kmac_test_vectors_sha3_256	29.281m	332.527ms	1	1	100.00
		kmac_test_vectors_sha3_384	20.420s	3.640ms	1	1	100.00
		kmac_test_vectors_sha3_512	17.377m	772.713ms	1	1	100.00
		kmac_test_vectors_shake_128	25.898m	20.951ms	1	1	100.00
		kmac_test_vectors_shake_256	1.353m	11.043ms	1	1	100.00
		kmac_test_vectors_kmac	3.250s	173.477us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.170s	173.369us	1	1	100.00
V2	sideload	kmac_sideload	1.984m	5.433ms	1	1	100.00
V2	app	kmac_app	1.997m	7.885ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.692m	44.388ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	3.931m	18.674ms	1	1	100.00
V2	error	kmac_error	2.328m	9.955ms	1	1	100.00
V2	key_error	kmac_key_error	4.670s	1.850ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	5.860s	220.284us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	2.860s	211.707us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.810s	58.958us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	2.700s	176.643us	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.160s	59.896us	1	1	100.00
V2	stress_all	kmac_stress_all	11.588m	121.592ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.490s	24.763us	1	1	100.00
V2	alert_test	kmac_alert_test	1.630s	12.930us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.700s	481.953us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.700s	481.953us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.850s	40.789us	1	1	100.00
		kmac_csr_rw	1.750s	38.758us	1	1	100.00
		kmac_csr_aliasing	7.710s	2.085ms	1	1	100.00
		kmac_same_csr_outstanding	3.010s	224.456us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.850s	40.789us	1	1	100.00
		kmac_csr_rw	1.750s	38.758us	1	1	100.00
		kmac_csr_aliasing	7.710s	2.085ms	1	1	100.00
		kmac_same_csr_outstanding	3.010s	224.456us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.100s	60.214us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.100s	60.214us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.100s	60.214us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.100s	60.214us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.520s	151.564us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	54.180s	9.675ms	1	1	100.00
		kmac_tl_intg_err	2.720s	127.992us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.720s	127.992us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.160s	59.896us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.006m	19.805ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.984m	5.433ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.100s	60.214us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	54.180s	9.675ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	54.180s	9.675ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	54.180s	9.675ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.006m	19.805ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.160s	59.896us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	54.180s	9.675ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.263m	1.485ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.006m	19.805ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.840s	19.887us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.102290214911873572975783435785343643808411134784028586109651641139071306869827
      Line 80, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  19886863 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
        UVM_INFO @  19886863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---