KMAC/UNMASKED Simulation Results

Wednesday May 28 2025 18:36:19 UTC

GitHub Revision: 645424b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	25.960s	2.401ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.930s	245.258us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.740s	72.080us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	13.490s	1.264ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.280s	237.458us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.750s	132.850us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.740s	72.080us	1	1	100.00
		kmac_csr_aliasing	4.280s	237.458us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.740s	26.479us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.090s	103.980us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	20.290m	38.073ms	1	1	100.00
V2	burst_write	kmac_burst_write	9.677m	38.559ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	23.670s	2.440ms	1	1	100.00
		kmac_test_vectors_sha3_256	17.746m	16.716ms	1	1	100.00
		kmac_test_vectors_sha3_384	15.320s	1.723ms	1	1	100.00
		kmac_test_vectors_sha3_512	11.340s	747.663us	1	1	100.00
		kmac_test_vectors_shake_128	1.529m	2.150ms	1	1	100.00
		kmac_test_vectors_shake_256	1.637m	25.101ms	1	1	100.00
		kmac_test_vectors_kmac	2.920s	388.068us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.490s	61.857us	1	1	100.00
V2	sideload	kmac_sideload	2.612m	101.167ms	1	1	100.00
V2	app	kmac_app	2.943m	30.010ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.114m	21.733ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	3.273m	79.530ms	1	1	100.00
V2	error	kmac_error	2.315m	3.088ms	1	1	100.00
V2	key_error	kmac_key_error	6.890s	3.235ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	39.670s	10.087ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	22.260s	3.383ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	9.960s	441.947us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	29.330s	18.417ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.790s	99.539us	1	1	100.00
V2	stress_all	kmac_stress_all	1.669m	10.176ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.790s	42.512us	1	1	100.00
V2	alert_test	kmac_alert_test	1.730s	13.890us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.440s	229.470us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.440s	229.470us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.930s	245.258us	1	1	100.00
		kmac_csr_rw	1.740s	72.080us	1	1	100.00
		kmac_csr_aliasing	4.280s	237.458us	1	1	100.00
		kmac_same_csr_outstanding	2.370s	53.426us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.930s	245.258us	1	1	100.00
		kmac_csr_rw	1.740s	72.080us	1	1	100.00
		kmac_csr_aliasing	4.280s	237.458us	1	1	100.00
		kmac_same_csr_outstanding	2.370s	53.426us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.910s	65.286us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.910s	65.286us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.910s	65.286us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.910s	65.286us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.720s	88.700us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	22.430s	5.484ms	1	1	100.00
		kmac_tl_intg_err	2.550s	200.684us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.550s	200.684us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.790s	99.539us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	25.960s	2.401ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	2.612m	101.167ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.910s	65.286us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	22.430s	5.484ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	22.430s	5.484ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	22.430s	5.484ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	25.960s	2.401ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.790s	99.539us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	22.430s	5.484ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.377m	20.208ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	25.960s	2.401ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	48.380s	8.434ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.22224754231069911070315647350304619266545921375924582801162018805656878467451
      Line 80, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10086908045 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x34a18000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
        UVM_INFO @ 10086908045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---