RV_DM/USE_JTAG_INTERFACE Simulation Results

Wednesday May 28 2025 18:36:19 UTC

GitHub Revision: 645424b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 3.460s 2.348ms 1 1 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 1.670s 173.806us 1 1 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 1.700s 653.858us 1 1 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 11.570s 15.536ms 1 1 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 1.940s 553.521us 1 1 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 13.150s 12.538ms 1 1 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 6.590s 2.937ms 1 1 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 15.860s 15.271ms 1 1 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 13.250s 58.006ms 1 1 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 1.650s 381.975us 1 1 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 1.880s 158.971us 1 1 100.00
V1 cmderr_exception rv_dm_cmderr_exception 1.980s 448.745us 1 1 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 1.890s 425.918us 1 1 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 1.790s 82.105us 1 1 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 3.070s 805.914us 1 1 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.720s 365.344us 1 1 100.00
V1 halt_resume rv_dm_halt_resume_whereto 1.650s 249.870us 1 1 100.00
V1 progbuf_busy rv_dm_cmderr_busy 1.650s 381.975us 1 1 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 1.800s 286.541us 1 1 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 1.760s 166.144us 1 1 100.00
V1 progbuf_exception rv_dm_cmderr_exception 1.980s 448.745us 1 1 100.00
V1 rom_read_access rv_dm_rom_read_access 1.840s 54.134us 1 1 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.850s 195.159us 1 1 100.00
V1 csr_rw rv_dm_csr_rw 2.210s 219.179us 1 1 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 25.070s 14.624ms 1 1 100.00
V1 csr_aliasing rv_dm_csr_aliasing 21.480s 3.573ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 1.530s 16.526us 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 21.480s 3.573ms 1 1 100.00
rv_dm_csr_rw 2.210s 219.179us 1 1 100.00
V1 mem_walk rv_dm_mem_walk 1.640s 74.563us 1 1 100.00
V1 mem_partial_access rv_dm_mem_partial_access 1.650s 87.814us 1 1 100.00
V1 TOTAL 26 27 96.30
V2 idcode rv_dm_smoke 3.460s 2.348ms 1 1 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 1.880s 326.866us 1 1 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.700s 120.604us 1 1 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 1.990s 242.400us 1 1 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 1.990s 765.973us 1 1 100.00
V2 sba rv_dm_sba_tl_access 3.980s 2.577ms 1 1 100.00
rv_dm_delayed_resp_sba_tl_access 2.020s 288.170us 0 1 0.00
V2 bad_sba rv_dm_bad_sba_tl_access 2.930s 2.544ms 1 1 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 1.750s 284.747us 0 1 0.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 1.940s 515.055us 1 1 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 3.110s 1.725ms 1 1 100.00
V2 ndmreset_req rv_dm_ndmreset_req 1.660s 228.079us 1 1 100.00
V2 hart_unavail rv_dm_hart_unavail 1.640s 157.218us 1 1 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 11.250s 4.943ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 1.850s 22.757us 0 1 0.00
V2 hartsel_warl rv_dm_hartsel_warl 1.620s 202.938us 1 1 100.00
V2 stress_all rv_dm_stress_all 3.210s 2.860ms 1 1 100.00
V2 alert_test rv_dm_alert_test 1.740s 33.672us 1 1 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 1.770s 23.201us 0 1 0.00
V2 tl_d_illegal_access rv_dm_tl_errors 1.770s 23.201us 0 1 0.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 21.480s 3.573ms 1 1 100.00
rv_dm_csr_hw_reset 2.850s 195.159us 1 1 100.00
rv_dm_csr_rw 2.210s 219.179us 1 1 100.00
rv_dm_same_csr_outstanding 4.000s 999.859us 1 1 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 21.480s 3.573ms 1 1 100.00
rv_dm_csr_hw_reset 2.850s 195.159us 1 1 100.00
rv_dm_csr_rw 2.210s 219.179us 1 1 100.00
rv_dm_same_csr_outstanding 4.000s 999.859us 1 1 100.00
V2 TOTAL 15 19 78.95
V2S tl_intg_err rv_dm_sec_cm 2.060s 612.443us 1 1 100.00
rv_dm_tl_intg_err 14.250s 8.331ms 1 1 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 14.250s 8.331ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 3.110s 1.725ms 1 1 100.00
rv_dm_debug_disabled 1.870s 89.305us 1 1 100.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 3.110s 1.725ms 1 1 100.00
rv_dm_debug_disabled 1.870s 89.305us 1 1 100.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 3.460s 2.348ms 1 1 100.00
V2S sec_cm_dm_en_ctrl_lc_gated rv_dm_buffered_enable 2.010s 593.062us 1 1 100.00
V2S sec_cm_sba_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.630s 99.755us 1 1 100.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.630s 99.755us 1 1 100.00
V2S sec_cm_exec_ctrl_mubi rv_dm_buffered_enable 2.010s 593.062us 1 1 100.00
V2S TOTAL 5 5 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 1.690s 40.068us 0 1 0.00
V3 TOTAL 0 1 0.00
Unmapped tests rv_dm_scanmode 1.720s 44.992us 1 1 100.00
TOTAL 47 53 88.68

Failure Buckets