RV_TIMER Simulation Results

Wednesday May 28 2025 18:36:19 UTC

GitHub Revision: 645424b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.590s	14.314us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.590s	57.393us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.580s	42.161us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.290s	299.031us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.660s	62.895us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	2.020s	84.869us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.580s	42.161us	1	1	100.00
		rv_timer_csr_aliasing	1.660s	62.895us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	7.650s	13.671ms	1	1	100.00
V2	disabled	rv_timer_disabled	1.830s	841.162us	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	3.478m	344.869ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	3.478m	344.869ms	1	1	100.00
V2	stress	rv_timer_stress_all	3.200s	2.757ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.600s	45.953us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.510s	11.961us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.060s	511.114us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.060s	511.114us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.590s	57.393us	1	1	100.00
		rv_timer_csr_rw	1.580s	42.161us	1	1	100.00
		rv_timer_csr_aliasing	1.660s	62.895us	1	1	100.00
		rv_timer_same_csr_outstanding	1.650s	53.149us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.590s	57.393us	1	1	100.00
		rv_timer_csr_rw	1.580s	42.161us	1	1	100.00
		rv_timer_csr_aliasing	1.660s	62.895us	1	1	100.00
		rv_timer_same_csr_outstanding	1.650s	53.149us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.750s	71.181us	1	1	100.00
		rv_timer_tl_intg_err	1.980s	148.327us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.980s	148.327us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	5.100s	639.378us	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.910s	14.146us	1	1	100.00
		rv_timer_max	1.640s	11.452us	1	1	100.00
		TOTAL			19	19	100.00