SPI_DEVICE/1R1W Simulation Results

Wednesday May 28 2025 18:36:19 UTC

GitHub Revision: 645424b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	56.190s	22.932ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.800s	73.931us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.350s	55.985us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	10.450s	7.571ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	7.050s	1.420ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.410s	102.628us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.350s	55.985us	1	1	100.00
		spi_device_csr_aliasing	7.050s	1.420ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.570s	37.885us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.290s	34.937us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.650s	111.477us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.750s	3.339us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.690s	5.177us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	3.160s	171.269us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	3.160s	171.269us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	2.830s	888.572us	1	1	100.00
		spi_device_tpm_sts_read	1.500s	73.000us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	4.590s	1.658ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	3.770s	691.035us	1	1	100.00
		spi_device_flash_all	1.640s	25.209us	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	5.480s	2.146ms	1	1	100.00
		spi_device_flash_all	1.640s	25.209us	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	5.480s	2.146ms	1	1	100.00
		spi_device_flash_all	1.640s	25.209us	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.640s	25.209us	1	1	100.00
V2	cmd_read_status	spi_device_intercept	5.650s	570.920us	1	1	100.00
		spi_device_flash_all	1.640s	25.209us	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	5.650s	570.920us	1	1	100.00
		spi_device_flash_all	1.640s	25.209us	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	5.650s	570.920us	1	1	100.00
		spi_device_flash_all	1.640s	25.209us	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	5.650s	570.920us	1	1	100.00
		spi_device_flash_all	1.640s	25.209us	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	5.650s	570.920us	1	1	100.00
		spi_device_flash_all	1.640s	25.209us	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	4.600s	1.494ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	25.160s	4.347ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	25.160s	4.347ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	25.160s	4.347ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	20.670s	3.798ms	1	1	100.00
		spi_device_read_buffer_direct	3.580s	98.020us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	25.160s	4.347ms	1	1	100.00
		spi_device_flash_all	1.640s	25.209us	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.640s	25.209us	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.640s	25.209us	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	5.100s	3.395ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	5.100s	3.395ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	56.190s	22.932ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	24.540s	6.674ms	1	1	100.00
V2	stress_all	spi_device_stress_all	2.736m	231.662ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.530s	24.677us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.680s	11.741us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.820s	94.185us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.820s	94.185us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.800s	73.931us	1	1	100.00
		spi_device_csr_rw	2.350s	55.985us	1	1	100.00
		spi_device_csr_aliasing	7.050s	1.420ms	1	1	100.00
		spi_device_same_csr_outstanding	3.130s	576.216us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.800s	73.931us	1	1	100.00
		spi_device_csr_rw	2.350s	55.985us	1	1	100.00
		spi_device_csr_aliasing	7.050s	1.420ms	1	1	100.00
		spi_device_same_csr_outstanding	3.130s	576.216us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.920s	397.400us	1	1	100.00
		spi_device_tl_intg_err	5.370s	390.068us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	5.370s	390.068us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.110m	45.161ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.97911043627411217632036887327039185719083005375002685931650692073925205638034
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   2877795 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[7])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   2877795 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   2877795 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[903])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.9764541154036996714421232793797497340303661182550837728880088872848716935923
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   2544066 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf53afc [111101010011101011111100] vs 0x0 [0])
        UVM_ERROR @   2641066 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x61daa7 [11000011101101010100111] vs 0x0 [0])
        UVM_ERROR @   2666066 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x126e9 [10010011011101001] vs 0x0 [0])
        UVM_ERROR @   2746066 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa2c768 [101000101100011101101000] vs 0x0 [0])
        UVM_ERROR @   2796066 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2a5603 [1010100101011000000011] vs 0x0 [0])