SPI_DEVICE/2P Simulation Results

Wednesday May 28 2025 18:36:19 UTC

GitHub Revision: 645424b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	58.630s	53.337ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.900s	107.547us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.470s	562.787us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	18.870s	7.216ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	6.780s	2.341ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.440s	115.053us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.470s	562.787us	1	1	100.00
		spi_device_csr_aliasing	6.780s	2.341ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.660s	16.433us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.930s	374.493us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.700s	21.623us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.960s	26.297us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	1.630s	21.226us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	2.940s	1.243ms	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.940s	1.243ms	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	10.140s	24.660ms	1	1	100.00
		spi_device_tpm_sts_read	1.680s	57.751us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	17.180s	12.836ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	15.730s	10.578ms	1	1	100.00
		spi_device_flash_all	22.540s	1.695ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	3.310s	412.656us	1	1	100.00
		spi_device_flash_all	22.540s	1.695ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	3.310s	412.656us	1	1	100.00
		spi_device_flash_all	22.540s	1.695ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	22.540s	1.695ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	19.720s	3.807ms	1	1	100.00
		spi_device_flash_all	22.540s	1.695ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	19.720s	3.807ms	1	1	100.00
		spi_device_flash_all	22.540s	1.695ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	19.720s	3.807ms	1	1	100.00
		spi_device_flash_all	22.540s	1.695ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	19.720s	3.807ms	1	1	100.00
		spi_device_flash_all	22.540s	1.695ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	19.720s	3.807ms	1	1	100.00
		spi_device_flash_all	22.540s	1.695ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	23.640s	47.824ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	1.037m	119.478ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.037m	119.478ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.037m	119.478ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	5.550s	168.178us	1	1	100.00
		spi_device_read_buffer_direct	6.800s	4.137ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.037m	119.478ms	1	1	100.00
		spi_device_flash_all	22.540s	1.695ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	22.540s	1.695ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	22.540s	1.695ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.300s	116.587us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.300s	116.587us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	58.630s	53.337ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	34.960s	2.560ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.910s	86.372us	1	1	100.00
V2	alert_test	spi_device_alert_test	1.710s	14.285us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.510s	116.391us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.280s	247.777us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.280s	247.777us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.900s	107.547us	1	1	100.00
		spi_device_csr_rw	2.470s	562.787us	1	1	100.00
		spi_device_csr_aliasing	6.780s	2.341ms	1	1	100.00
		spi_device_same_csr_outstanding	3.870s	61.251us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.900s	107.547us	1	1	100.00
		spi_device_csr_rw	2.470s	562.787us	1	1	100.00
		spi_device_csr_aliasing	6.780s	2.341ms	1	1	100.00
		spi_device_same_csr_outstanding	3.870s	61.251us	1	1	100.00
V2		TOTAL			22	22	100.00
V2S	tl_intg_err	spi_device_sec_cm	2.280s	301.146us	1	1	100.00
		spi_device_tl_intg_err	16.430s	2.155ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	16.430s	2.155ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	26.770s	6.290ms	1	1	100.00
		TOTAL			33	33	100.00