| V1 |
smoke |
spi_host_smoke |
11.000s |
1.669ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
spi_host_csr_hw_reset |
9.000s |
16.824us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
spi_host_csr_rw |
9.000s |
19.677us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
spi_host_csr_bit_bash |
10.000s |
236.408us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
spi_host_csr_aliasing |
7.000s |
16.119us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
spi_host_csr_mem_rw_with_rand_reset |
4.000s |
19.564us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
spi_host_csr_rw |
9.000s |
19.677us |
1 |
1 |
100.00 |
|
|
spi_host_csr_aliasing |
7.000s |
16.119us |
1 |
1 |
100.00 |
| V1 |
mem_walk |
spi_host_mem_walk |
10.000s |
36.729us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
spi_host_mem_partial_access |
10.000s |
24.476us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
performance |
spi_host_performance |
4.000s |
20.496us |
1 |
1 |
100.00 |
| V2 |
error_event_intr |
spi_host_overflow_underflow |
47.000s |
6.182ms |
1 |
1 |
100.00 |
|
|
spi_host_error_cmd |
4.000s |
19.128us |
1 |
1 |
100.00 |
|
|
spi_host_event |
11.000s |
11.372ms |
1 |
1 |
100.00 |
| V2 |
clock_rate |
spi_host_speed |
6.000s |
349.004us |
1 |
1 |
100.00 |
| V2 |
speed |
spi_host_speed |
6.000s |
349.004us |
1 |
1 |
100.00 |
| V2 |
chip_select_timing |
spi_host_speed |
6.000s |
349.004us |
1 |
1 |
100.00 |
| V2 |
sw_reset |
spi_host_sw_reset |
9.000s |
256.739us |
1 |
1 |
100.00 |
| V2 |
passthrough_mode |
spi_host_passthrough_mode |
4.000s |
21.869us |
1 |
1 |
100.00 |
| V2 |
cpol_cpha |
spi_host_speed |
6.000s |
349.004us |
1 |
1 |
100.00 |
| V2 |
full_cycle |
spi_host_speed |
6.000s |
349.004us |
1 |
1 |
100.00 |
| V2 |
duplex |
spi_host_smoke |
11.000s |
1.669ms |
1 |
1 |
100.00 |
| V2 |
tx_rx_only |
spi_host_smoke |
11.000s |
1.669ms |
1 |
1 |
100.00 |
| V2 |
stress_all |
spi_host_stress_all |
12.000s |
540.678us |
1 |
1 |
100.00 |
| V2 |
spien |
spi_host_spien |
8.000s |
970.590us |
1 |
1 |
100.00 |
| V2 |
stall |
spi_host_status_stall |
55.000s |
15.860ms |
1 |
1 |
100.00 |
| V2 |
Idlecsbactive |
spi_host_idlecsbactive |
4.000s |
47.921us |
1 |
1 |
100.00 |
| V2 |
data_fifo_status |
spi_host_overflow_underflow |
47.000s |
6.182ms |
1 |
1 |
100.00 |
| V2 |
alert_test |
spi_host_alert_test |
4.000s |
17.433us |
1 |
1 |
100.00 |
| V2 |
intr_test |
spi_host_intr_test |
10.000s |
29.202us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
spi_host_tl_errors |
12.000s |
115.112us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
spi_host_tl_errors |
12.000s |
115.112us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
spi_host_csr_hw_reset |
9.000s |
16.824us |
1 |
1 |
100.00 |
|
|
spi_host_csr_rw |
9.000s |
19.677us |
1 |
1 |
100.00 |
|
|
spi_host_csr_aliasing |
7.000s |
16.119us |
1 |
1 |
100.00 |
|
|
spi_host_same_csr_outstanding |
6.000s |
40.565us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
spi_host_csr_hw_reset |
9.000s |
16.824us |
1 |
1 |
100.00 |
|
|
spi_host_csr_rw |
9.000s |
19.677us |
1 |
1 |
100.00 |
|
|
spi_host_csr_aliasing |
7.000s |
16.119us |
1 |
1 |
100.00 |
|
|
spi_host_same_csr_outstanding |
6.000s |
40.565us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
15 |
15 |
100.00 |
| V2S |
tl_intg_err |
spi_host_tl_intg_err |
12.000s |
248.528us |
1 |
1 |
100.00 |
|
|
spi_host_sec_cm |
4.000s |
142.080us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
spi_host_tl_intg_err |
12.000s |
248.528us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
|
Unmapped tests |
spi_host_upper_range_clkdiv |
6.433m |
42.713ms |
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
26 |
26 |
100.00 |