SRAM_CTRL/MAIN Simulation Results

Wednesday May 28 2025 18:36:19 UTC

GitHub Revision: 645424b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	24.680s	2.257ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.530s	18.737us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.530s	10.964us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.930s	29.780us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.700s	16.669us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.340s	363.785us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.530s	10.964us	1	1	100.00
		sram_ctrl_csr_aliasing	1.700s	16.669us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	4.049m	18.739ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.847m	10.216ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	3.792m	27.499ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.054m	4.114ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	21.332m	52.587ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	7.889m	49.197ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	17.500s	14.333ms	1	1	100.00
V2	executable	sram_ctrl_executable	12.594m	63.337ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	5.030s	751.912us	1	1	100.00
		sram_ctrl_partial_access_b2b	4.128m	27.252ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	44.370s	757.033us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	8.800s	1.454ms	1	1	100.00
		sram_ctrl_throughput_w_readback	9.230s	4.473ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	7.756m	20.947ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.570s	679.940us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	37.559m	122.166ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.410s	14.944us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.220s	71.124us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.220s	71.124us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.530s	18.737us	1	1	100.00
		sram_ctrl_csr_rw	1.530s	10.964us	1	1	100.00
		sram_ctrl_csr_aliasing	1.700s	16.669us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.870s	113.997us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.530s	18.737us	1	1	100.00
		sram_ctrl_csr_rw	1.530s	10.964us	1	1	100.00
		sram_ctrl_csr_aliasing	1.700s	16.669us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.870s	113.997us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	15.060s	7.357ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.650s	5.243us	0	1	0.00
		sram_ctrl_tl_intg_err	3.360s	332.642us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.650s	5.243us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.360s	332.642us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	7.756m	20.947ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	7.756m	20.947ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.530s	10.964us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	12.594m	63.337ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	12.594m	63.337ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	12.594m	63.337ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	17.500s	14.333ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	6.050s	675.114us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	15.060s	7.357ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.840s	2.647ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	24.680s	2.257ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	24.680s	2.257ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	12.594m	63.337ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.650s	5.243us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	17.500s	14.333ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.650s	5.243us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.650s	5.243us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	24.680s	2.257ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.650s	5.243us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	7.700s	1.051ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.63777383077091969598279692191338654820414782156380678600064687205806890507855
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   5243451 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   5243451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---