SRAM_CTRL/RET Simulation Results

Wednesday May 28 2025 18:36:19 UTC

GitHub Revision: 645424b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	7.110s	122.697us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.640s	31.160us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.640s	14.842us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.560s	242.912us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.610s	21.813us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.110s	215.382us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.640s	14.842us	1	1	100.00
		sram_ctrl_csr_aliasing	1.610s	21.813us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.750s	233.732us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.120s	317.465us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	10.669m	38.782ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.192m	32.473ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	32.430s	2.968ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	12.803m	15.867ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.600s	124.054us	1	1	100.00
V2	executable	sram_ctrl_executable	4.376m	8.928ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	16.540s	4.576ms	1	1	100.00
		sram_ctrl_partial_access_b2b	5.925m	18.324ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	15.820s	321.446us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	46.490s	1.042ms	1	1	100.00
		sram_ctrl_throughput_w_readback	4.170s	182.862us	1	1	100.00
V2	regwen	sram_ctrl_regwen	9.511m	14.730ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.850s	53.940us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	35.204m	42.087ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.800s	20.748us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.780s	570.017us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.780s	570.017us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.640s	31.160us	1	1	100.00
		sram_ctrl_csr_rw	1.640s	14.842us	1	1	100.00
		sram_ctrl_csr_aliasing	1.610s	21.813us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.620s	46.831us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.640s	31.160us	1	1	100.00
		sram_ctrl_csr_rw	1.640s	14.842us	1	1	100.00
		sram_ctrl_csr_aliasing	1.610s	21.813us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.620s	46.831us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.370s	3.405ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.900s	26.618us	0	1	0.00
		sram_ctrl_tl_intg_err	3.110s	1.469ms	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.900s	26.618us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.110s	1.469ms	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	9.511m	14.730ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	9.511m	14.730ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.640s	14.842us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	4.376m	8.928ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	4.376m	8.928ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	4.376m	8.928ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.600s	124.054us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.060s	39.356us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.370s	3.405ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.830s	100.332us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	7.110s	122.697us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	7.110s	122.697us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	4.376m	8.928ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.900s	26.618us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.600s	124.054us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.900s	26.618us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.900s	26.618us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	7.110s	122.697us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.900s	26.618us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	17.930s	3.097ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.97853825600749302592050729733351099843065597998680584034053754585393869021705
      Line 98, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  26617560 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  26617560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---