SYSRST_CTRL Simulation Results

Wednesday May 28 2025 18:36:19 UTC

GitHub Revision: 645424b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 3.030s 2.131ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 6.850s 2.472ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 4.420s 2.210ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 2.610s 2.353ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 8.380s 6.048ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 9.100s 2.057ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 36.000s 57.490ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 3.670s 2.537ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 2.470s 2.119ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 9.100s 2.057ms 1 1 100.00
sysrst_ctrl_csr_aliasing 3.670s 2.537ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 1.671m 110.152ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 9.170s 27.607ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 7.820s 3.165ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 6.320s 3.683ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 4.000s 2.517ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 3.550s 2.129ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 7.090s 3.100ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 2.200s 2.656ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 1.469m 1.904s 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 50.150s 37.453ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 1.455m 514.834ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 2.250s 2.076ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 2.510s 2.041ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 5.220s 2.242ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 5.220s 2.242ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 8.380s 6.048ms 1 1 100.00
sysrst_ctrl_csr_rw 9.100s 2.057ms 1 1 100.00
sysrst_ctrl_csr_aliasing 3.670s 2.537ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 5.170s 4.701ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 8.380s 6.048ms 1 1 100.00
sysrst_ctrl_csr_rw 9.100s 2.057ms 1 1 100.00
sysrst_ctrl_csr_aliasing 3.670s 2.537ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 5.170s 4.701ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 1.295m 42.013ms 1 1 100.00
sysrst_ctrl_tl_intg_err 8.650s 22.456ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 8.650s 22.456ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 14.170s 5.897ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00