UART Simulation Results

Wednesday May 28 2025 18:36:19 UTC

GitHub Revision: 645424b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.020s	572.684us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.770s	72.486us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.500s	13.714us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.150s	473.623us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.630s	21.876us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.540s	30.141us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.500s	13.714us	1	1	100.00
		uart_csr_aliasing	1.630s	21.876us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	24.470s	129.750ms	1	1	100.00
V2	parity	uart_smoke	2.020s	572.684us	1	1	100.00
		uart_tx_rx	24.470s	129.750ms	1	1	100.00
V2	parity_error	uart_intr	1.072m	47.871ms	1	1	100.00
		uart_rx_parity_err	11.280s	11.850ms	1	1	100.00
V2	watermark	uart_tx_rx	24.470s	129.750ms	1	1	100.00
		uart_intr	1.072m	47.871ms	1	1	100.00
V2	fifo_full	uart_fifo_full	1.793m	162.016ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	4.395m	188.223ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	1.925m	192.045ms	1	1	100.00
V2	rx_frame_err	uart_intr	1.072m	47.871ms	1	1	100.00
V2	rx_break_err	uart_intr	1.072m	47.871ms	1	1	100.00
V2	rx_timeout	uart_intr	1.072m	47.871ms	1	1	100.00
V2	perf	uart_perf	2.143m	3.277ms	1	1	100.00
V2	sys_loopback	uart_loopback	4.310s	1.170ms	1	1	100.00
V2	line_loopback	uart_loopback	4.310s	1.170ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	8.170s	24.134ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	3.480s	1.614ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	4.170s	2.333ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	43.240s	6.444ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	8.765m	105.668ms	1	1	100.00
V2	stress_all	uart_stress_all	1.743m	157.651ms	1	1	100.00
V2	alert_test	uart_alert_test	1.690s	30.538us	1	1	100.00
V2	intr_test	uart_intr_test	1.960s	16.089us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.810s	135.837us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.810s	135.837us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.770s	72.486us	1	1	100.00
		uart_csr_rw	1.500s	13.714us	1	1	100.00
		uart_csr_aliasing	1.630s	21.876us	1	1	100.00
		uart_same_csr_outstanding	1.560s	97.431us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.770s	72.486us	1	1	100.00
		uart_csr_rw	1.500s	13.714us	1	1	100.00
		uart_csr_aliasing	1.630s	21.876us	1	1	100.00
		uart_same_csr_outstanding	1.560s	97.431us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.860s	49.638us	1	1	100.00
		uart_tl_intg_err	2.660s	76.652us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.660s	76.652us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	22.300s	9.519ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00