CHIP Simulation Results

Wednesday May 28 2025 18:36:19 UTC

GitHub Revision: `645424b`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.818m	2.783ms	1	1	100.00
		chip_sw_example_rom	1.108m	2.908ms	1	1	100.00
		chip_sw_example_manufacturer	3.039m	2.957ms	1	1	100.00
		chip_sw_example_concurrency	2.383m	2.710ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	2.166m	4.758ms	1	1	100.00
V1	csr_rw	chip_csr_rw	3.048m	4.938ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	4.084m	4.994ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	50.602m	28.730ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	7.714m	9.518ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	50.602m	28.730ms	1	1	100.00
		chip_csr_rw	3.048m	4.938ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	6.550s	212.701us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.367m	4.262ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.367m	4.262ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.367m	4.262ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.661m	3.838ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.661m	3.838ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.697m	4.255ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.440m	4.262ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.980m	4.570ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	27.734m	12.756ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	14.765m	8.108ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	11.504m	8.829ms	1	1	100.00
V1		TOTAL			18	18	100.00
V2	chip_pin_mux	chip_padctrl_attributes	2.912m	5.302ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.912m	5.302ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.644m	2.911ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	5.192m	5.204ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.357m	2.980ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	2.885m	3.430ms	1	1	100.00
		chip_tap_straps_testunlock0	1.848m	2.408ms	1	1	100.00
		chip_tap_straps_rma	1.709m	3.251ms	1	1	100.00
		chip_tap_straps_prod	14.958m	15.084ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.582m	2.413ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	12.328m	9.151ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	7.349m	6.422ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	7.349m	6.422ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	9.431m	8.268ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	35.847m	21.483ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.349m	4.109ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.912m	5.277ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.448m	18.102ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.936m	3.181ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	10.950m	6.232ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.547m	2.635ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	19.343m	10.126ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.525m	2.897ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.417m	4.704ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.538m	2.995ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	2.810m	3.423ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	9.691m	8.473ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.872m	4.916ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	1.944m	2.365ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.872m	4.916ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.209m	2.558ms	1	1	100.00
		chip_sw_aes_smoketest	2.694m	2.650ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.007m	3.174ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.937m	2.737ms	1	1	100.00
		chip_sw_csrng_smoketest	2.466m	2.757ms	1	1	100.00
		chip_sw_entropy_src_smoketest	4.939m	3.618ms	1	1	100.00
		chip_sw_gpio_smoketest	3.792m	3.820ms	1	1	100.00
		chip_sw_hmac_smoketest	2.662m	3.700ms	1	1	100.00
		chip_sw_kmac_smoketest	3.382m	2.673ms	1	1	100.00
		chip_sw_otbn_smoketest	7.589m	5.279ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	2.837m	5.853ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.176m	4.810ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.167m	2.506ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.448m	3.126ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.337m	3.327ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.179m	2.403ms	1	1	100.00
		chip_sw_uart_smoketest	2.534m	2.928ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	1.691m	3.144ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.184m	3.215ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.061h	60.239ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	39.050m	14.498ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.409m	5.549ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.702m	3.195ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.313m	3.309ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.838h	53.324ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.881h	57.216ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	48.350s	3.015ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	48.350s	3.015ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	50.602m	28.730ms	1	1	100.00
		chip_same_csr_outstanding	17.484m	16.520ms	1	1	100.00
		chip_csr_hw_reset	2.166m	4.758ms	1	1	100.00
		chip_csr_rw	3.048m	4.938ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	50.602m	28.730ms	1	1	100.00
		chip_same_csr_outstanding	17.484m	16.520ms	1	1	100.00
		chip_csr_hw_reset	2.166m	4.758ms	1	1	100.00
		chip_csr_rw	3.048m	4.938ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	4.870s	38.875us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	5.030s	52.458us	1	1	100.00
		xbar_smoke_large_delays	42.550s	6.148ms	1	1	100.00
		xbar_smoke_slow_rsp	44.360s	5.159ms	1	1	100.00
		xbar_random_zero_delays	13.260s	222.248us	1	1	100.00
		xbar_random_large_delays	2.260m	22.358ms	1	1	100.00
		xbar_random_slow_rsp	1.716m	12.195ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	18.900s	224.168us	1	1	100.00
		xbar_error_and_unmapped_addr	35.630s	1.540ms	1	1	100.00
V2	xbar_error_cases	xbar_error_random	11.440s	512.659us	1	1	100.00
		xbar_error_and_unmapped_addr	35.630s	1.540ms	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	31.090s	705.638us	1	1	100.00
		xbar_access_same_device_slow_rsp	10.937m	75.320ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	23.050s	367.926us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	1.881m	2.283ms	1	1	100.00
		xbar_stress_all_with_error	1.985m	2.696ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	3.042m	2.568ms	1	1	100.00
		xbar_stress_all_with_reset_error	45.250s	175.685us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	39.050m	14.498ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	37.306m	28.685ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	38.923m	15.849ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	31.746m	11.070ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	40.646m	15.216ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	39.203m	15.351ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	40.818m	16.035ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	38.424m	14.969ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	30.720s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	31.400s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	27.310s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	29.470s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	27.640s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	27.630s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	31.650s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	34.100s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	30.050s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	27.240s	10.120us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	27.860s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	24.970s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	26.110s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	26.240s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	26.580s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	27.190s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	26.230s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	25.830s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	26.850s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	26.060s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	25.890s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	26.990s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	26.200s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	25.720s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	25.940s	10.120us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	28.642m	11.835ms	1	1	100.00
		rom_e2e_asm_init_dev	39.299m	15.926ms	1	1	100.00
		rom_e2e_asm_init_prod	37.101m	16.149ms	1	1	100.00
		rom_e2e_asm_init_prod_end	38.599m	15.427ms	1	1	100.00
		rom_e2e_asm_init_rma	36.619m	14.685ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	35.712m	14.542ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	34.938m	15.657ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	35.808m	14.956ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	38.088m	15.803ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	43.160m	35.035ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	43.160m	35.035ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.501m	2.648ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.936m	3.181ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.016m	2.683ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.242m	3.125ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	24.119m	11.521ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	3.561m	3.359ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	5.692m	5.370ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	6.248m	5.258ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	9.423m	6.021ms	1	1	100.00
		chip_plic_all_irqs_10	4.621m	4.396ms	1	1	100.00
		chip_plic_all_irqs_20	5.921m	4.256ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.372m	3.189ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	13.811m	13.261ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.097m	3.622ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	1.953m	3.220ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	8.764m	8.783ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	13.318m	6.866ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	15.763m	7.449ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	13.170m	7.490ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	1.901h	255.145ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	4.077m	4.402ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	2.837m	5.853ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	4.077m	4.402ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	8.833m	8.558ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	8.833m	8.558ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	6.132m	7.938ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	5.483m	5.376ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	8.821m	5.475ms	1	1	100.00
		chip_sw_aes_idle	2.242m	3.125ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.337m	3.071ms	1	1	100.00
		chip_sw_kmac_idle	2.321m	3.174ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.420m	3.589ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	3.596m	3.380ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	3.210m	4.057ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	3.502m	4.004ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	8.889m	7.600ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.190m	4.445ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.702m	5.043ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.996m	3.976ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.662m	4.932ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.298m	3.319ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.856m	4.448ms	1	1	100.00
		chip_sw_ast_clk_outputs	9.431m	8.268ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	9.304m	10.105ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.996m	3.976ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.662m	4.932ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.349m	4.109ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.912m	5.277ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.448m	18.102ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.936m	3.181ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	10.950m	6.232ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.547m	2.635ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	19.343m	10.126ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.525m	2.897ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.417m	4.704ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.538m	2.995ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.214m	2.461ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	5.842m	4.601ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	9.279m	6.952ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	47.652m	24.520ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.478m	2.928ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.606m	3.706ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	9.974m	7.869ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.460m	3.654ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.275m	5.501ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	17.034m	19.698ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	4.766h	215.302ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	9.431m	8.268ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.106m	4.499ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.340m	3.119ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	6.248m	5.258ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	13.318m	6.866ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	16.404m	8.524ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.075m	2.726ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	4.983m	6.725ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.782m	2.560ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.021h	23.929ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.835m	2.668ms	1	1	100.00
		chip_sw_edn_entropy_reqs	9.085m	6.301ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.835m	2.668ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	16.404m	8.524ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	1.745m	1.921ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	15.832m	21.045ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.309m	5.635ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.912m	5.277ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.634m	4.489ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.349m	4.109ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	51.089m	42.133ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	15.832m	21.045ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.121m	3.136ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	28.231m	11.964ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.233m	5.813ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	51.089m	42.133ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.233m	5.813ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.233m	5.813ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.233m	5.813ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.233m	5.813ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	6.248m	5.258ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	2.925m	9.706ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.109m	5.143ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	6.280m	4.816ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	6.280m	4.816ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.875m	3.229ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.547m	2.635ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.337m	3.071ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.772m	2.816ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	5.412m	3.825ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	4.674m	4.714ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	5.882m	5.043ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	5.439m	4.242ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.840m	4.618ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	28.231m	11.964ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	19.343m	10.126ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	13.097m	6.817ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	24.119m	11.521ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	29.115m	10.555ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.001m	2.681ms	1	1	100.00
		chip_sw_kmac_mode_kmac	3.088m	3.103ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.525m	2.897ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	28.231m	11.964ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	3.793m	6.259ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.489m	2.451ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	10.166m	6.074ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.321m	3.174ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	5.692m	5.370ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	2.885m	3.430ms	1	1	100.00
		chip_tap_straps_rma	1.709m	3.251ms	1	1	100.00
		chip_tap_straps_prod	14.958m	15.084ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.498m	3.183ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	3.793m	6.259ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	3.793m	6.259ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	3.793m	6.259ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	16.203m	8.799ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.233m	5.813ms	1	1	100.00
		chip_sw_flash_rma_unlocked	51.089m	42.133ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.478m	3.773ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.973m	6.980ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.207m	7.161ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	6.687m	6.137ms	1	1	100.00
		chip_sw_lc_ctrl_transition	3.793m	6.259ms	1	1	100.00
		chip_sw_keymgr_key_derivation	28.231m	11.964ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.174m	9.417ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	5.941m	6.996ms	1	1	100.00
		chip_prim_tl_access	2.925m	9.706ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	9.304m	10.105ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.190m	4.445ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.702m	5.043ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.996m	3.976ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.662m	4.932ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.298m	3.319ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.856m	4.448ms	1	1	100.00
		chip_tap_straps_dev	2.885m	3.430ms	1	1	100.00
		chip_tap_straps_rma	1.709m	3.251ms	1	1	100.00
		chip_tap_straps_prod	14.958m	15.084ms	1	1	100.00
		chip_rv_dm_lc_disabled	5.216m	12.887ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.317m	2.969ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.509m	3.862ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.384m	3.510ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.010m	3.253ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	26.280m	31.561ms	1	1	100.00
		chip_rv_dm_lc_disabled	5.216m	12.887ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.002h	48.585ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.095h	50.443ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	7.236m	6.401ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	59.376m	47.497ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	26.280m	31.561ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.021m	2.136ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.174m	2.412ms	1	1	100.00
		rom_volatile_raw_unlock	1.052m	1.976ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	51.651m	17.078ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.448m	18.102ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	8.821m	5.475ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	8.821m	5.475ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	8.821m	5.475ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.634m	3.235ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	3.793m	6.259ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	15.832m	21.045ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.634m	3.235ms	1	1	100.00
		chip_sw_keymgr_key_derivation	28.231m	11.964ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.284m	4.571ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.692m	3.015ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	15.832m	21.045ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.634m	3.235ms	1	1	100.00
		chip_sw_keymgr_key_derivation	28.231m	11.964ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.284m	4.571ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.692m	3.015ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	3.793m	6.259ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	3.737m	3.736ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.498m	3.183ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.478m	3.773ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.973m	6.980ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.207m	7.161ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	6.687m	6.137ms	1	1	100.00
		chip_sw_lc_ctrl_transition	3.793m	6.259ms	1	1	100.00
		chip_prim_tl_access	2.925m	9.706ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	2.925m	9.706ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	16.337m	8.116ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	5.643m	7.835ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	14.823m	23.461ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.156m	7.156ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	6.093m	7.370ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	5.608m	5.891ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	15.881m	23.396ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	11.332m	12.917ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	8.833m	8.558ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	9.467m	8.787ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	5.647m	4.491ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	5.643m	7.835ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.321m	4.233ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	34.213m	44.751ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.678m	5.602ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	3.890m	5.642ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	21.746m	20.131ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	11.077m	8.635ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	13.516m	11.860ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	19.921m	22.519ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.364m	3.241ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	6.248m	5.258ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.174m	9.417ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.174m	9.417ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	13.516m	11.860ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	21.746m	20.131ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	5.647m	4.491ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	2.837m	5.853ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	5.121m	4.233ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.934m	3.757ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.755m	4.282ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	13.811m	13.261ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.730m	2.754ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	6.248m	5.258ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	15.763m	7.449ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.894m	4.548ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.422m	4.559ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.086m	3.223ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.692m	3.015ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.934m	3.757ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.934m	3.757ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	9.412m	9.249ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	15.909m	13.902ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	5.121m	4.233ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	4.074m	4.921ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	4.428m	5.411ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	1.709m	3.251ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	5.216m	12.887ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	9.423m	6.021ms	1	1	100.00
		chip_plic_all_irqs_10	4.621m	4.396ms	1	1	100.00
		chip_plic_all_irqs_20	5.921m	4.256ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.813m	2.501ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.269m	3.276ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	39.050m	14.498ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	6.083m	6.570ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.721m	3.086ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.425m	3.488ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.592m	2.368ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	6.284m	4.571ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.417m	4.704ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	4.728m	6.643ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	7.186m	9.036ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	5.941m	6.996ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	6.248m	5.258ms	1	1	100.00
		chip_sw_data_integrity_escalation	7.349m	6.422ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	11.077m	8.635ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	16.850m	24.798ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	1.804m	2.440ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	4.098m	3.673ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	4.833m	4.819ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	16.850m	24.798ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	16.850m	24.798ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	39.073m	20.587ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	39.073m	20.587ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	3.632m	5.047ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	43.160m	35.035ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	1.915m	3.008ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	1.777m	2.334ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.813m	3.543ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.175m	3.711ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	17.106m	8.702ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.321h	31.709ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	29.138m	11.612ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.146m	2.714ms	1	1	100.00
V2		TOTAL			240	275	87.27
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.539m	2.674ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.536m	2.517ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	2.482h	71.267ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	14.339m	6.022ms	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	17.125m	11.535ms	1	1	100.00
		rom_e2e_jtag_debug_dev	17.791m	10.668ms	1	1	100.00
		rom_e2e_jtag_debug_rma	16.799m	10.367ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.369m	4.643ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.720m	3.842ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.800m	4.558ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	20.905s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.573m	5.192ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	5.502m	2.936ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	8.560m	4.014ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	10.587m	6.775ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.472m	2.158ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	9.145m	5.292ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.275m	2.300ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	5.529m	5.255ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	4.504m	5.799ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	5.457m	5.441ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	13.516m	11.860ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	17.125m	11.535ms	1	1	100.00
		rom_e2e_jtag_debug_dev	17.791m	10.668ms	1	1	100.00
		rom_e2e_jtag_debug_rma	16.799m	10.367ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	5.220m	4.552ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	6.248m	5.258ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.321h	37.927ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.321h	37.927ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	3.181m	3.741ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.661m	3.838ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	49.136m	19.495ms	1	1	100.00
V3		TOTAL			22	23	95.65
	Unmapped tests	chip_sival_flash_info_access	2.545m	2.808ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	6.633m	5.337ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.271m	2.822ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	3.598m	3.003ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.519m	3.608ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	9.962s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.653m	2.521ms	1	1	100.00
		TOTAL			288	325	88.62

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.111499080139527061263883166744331265372217243085861556529290532513940467367390
    Line 642, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.106928011122882022842175624775608606680109894887268203179970454772475334262061
    Line 622, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.20162972147707391547216720665901933910746140469743909829214954665497208971492
    Line 672, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.53013680829585035455347361895140394996705808964675932763235900794908853676516
    Line 607, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.84546206677754205503314529830563411747462229643401730711678930458383027517896
    Line 634, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.88352311238722583158113770080785229218758810694954115144640040803337917758000
    Line 565, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.113641702982351121972725799373132715520616030472337268336553237357960633003400
    Line 603, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.46187128537885872694333137734684855707495525069922942558739575982429764220801
    Line 617, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.104136631252451230116191696462634709289913953307898167638949403065343181299627
    Line 667, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.72189911834332895333208935158412461781940069057205558918694551301492554756281
    Line 602, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.51576108885587262629236046187033011155471353063357578329536729201504019233698
    Line 718, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.95301951046439571906872537852578103580155086819064756654212626856657834804014
    Line 628, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.104270300667578107986261232296199933438259634221609324391532987966755952919130
    Line 647, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.82607241927786284325893266130029148317357378814512779433715356193204072182466
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.157s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.81653694532536772054596247819870368403021313258735222040878227880226152187757
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 11.072s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.12214903782318274034354045036490709795201249724116198840347318243368359059658
    Line 720, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.111854607508188495731082434445780790924600173096742304431925399122278147873271
    Line 581, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.58377957015849706997958365215583324205951694285812953784654821987384264907994
    Line 811, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.108703701979419068330005643361427855243136639334445745257920812517075346747706
    Line 649, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.112926193917251868252183569836622623638478296498254459743861585912947956522124
    Line 429, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3085.980386 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3085.980386 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@103229) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.1377842476326906675078818500940784081250853665619207727763516266762154934549
Line 442, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 3757.051640 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@103229) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3757.051640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.110863644955545988395637853958396789126063298048426413196012020785442493352699
    Line 438, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 35035.363646 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 35035.363646 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.15960060418160449812043977907733334132512606273757455675140211293972210594272
    Line 404, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3358.920880 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 3358.920880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.80842738273838887515632724665978837016299148352990786787268686372063852048575
    Line 413, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3220.291256 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 3220.291256 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:587) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.52982329355902386705826632175080691299858850233049925831015766535338275854393
    Line 440, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 2726.193746 us: (cip_base_vseq.sv:587) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 2726.193746 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32565) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.99389590333405183647820345690287432208476906280701433588531800787458175855250
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 3015.152156 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32565) { a_addr: 'h1049c  a_data: 'hd9c7e9fc  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h9  a_opcode: 'h4  a_user: 'h199b0  d_param: 'h0  d_source: 'h9  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3015.152156 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.69719239650959737228715011829136780155117402823318689268473584921846756769631
    Line 423, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3195.209500 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3195.209500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.110257738597232434457794675794230006958536175246591656706277376728145522438369
    Line 428, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3309.075000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3309.075000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.50303328355612631344784412764190363468135004663698039964329000846147861457259
    Line 445, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 21483.393948 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 21483.393948 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.45751317407233146120940513748974741193043059703355969565172111002214605210472
    Line 743, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.111448954896188538008744679230779086304765616833203055505469803004580774195470
    Line 803, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```