ADC_CTRL Simulation Results

Thursday May 29 2025 18:32:25 UTC

GitHub Revision: 5c5f5a8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	4.030s	5.823ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.620s	1.122ms	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.630s	340.317us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	23.000s	14.523ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.730s	562.373us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.240s	406.748us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.630s	340.317us	1	1	100.00
		adc_ctrl_csr_aliasing	2.730s	562.373us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	3.417m	492.056ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	8.710m	326.181ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	13.866m	497.130ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	13.461m	497.075ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	5.262m	393.689ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	17.160m	619.904ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	4.172m	161.875ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	3.314m	513.185ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	10.800s	5.643ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	21.300s	23.851ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	2.449m	88.249ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	17.220m	10.000s	0	1	0.00
V2	alert_test	adc_ctrl_alert_test	1.700s	419.547us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.790s	369.717us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.950s	547.223us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.950s	547.223us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.620s	1.122ms	1	1	100.00
		adc_ctrl_csr_rw	2.630s	340.317us	1	1	100.00
		adc_ctrl_csr_aliasing	2.730s	562.373us	1	1	100.00
		adc_ctrl_same_csr_outstanding	3.460s	2.767ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.620s	1.122ms	1	1	100.00
		adc_ctrl_csr_rw	2.630s	340.317us	1	1	100.00
		adc_ctrl_csr_aliasing	2.730s	562.373us	1	1	100.00
		adc_ctrl_same_csr_outstanding	3.460s	2.767ms	1	1	100.00
V2		TOTAL			15	16	93.75
V2S	tl_intg_err	adc_ctrl_sec_cm	5.410s	8.485ms	1	1	100.00
		adc_ctrl_tl_intg_err	8.630s	4.436ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	8.630s	4.436ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	4.680s	2.316ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test adc_ctrl_stress_all has 1 failures.

    • 0.adc_ctrl_stress_all.70177039030471691077094332283896353313156242762854935159693171325462943119335
      Line 147, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all/latest/run.log

        UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---