CSRNG Simulation Results

Thursday May 29 2025 18:32:25 UTC

GitHub Revision: 5c5f5a8

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	7.000s	201.154us	1	1	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	6.000s	20.865us	1	1	100.00
V1	csr_rw	csrng_csr_rw	4.000s	53.803us	1	1	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	1.150m	6.484ms	1	1	100.00
V1	csr_aliasing	csrng_csr_aliasing	6.000s	36.351us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	6.000s	88.836us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	53.803us	1	1	100.00
		csrng_csr_aliasing	6.000s	36.351us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	interrupts	csrng_intr	6.000s	108.841us	1	1	100.00
V2	alerts	csrng_alert	17.000s	584.436us	1	1	100.00
V2	err	csrng_err	5.000s	39.936us	1	1	100.00
V2	cmds	csrng_cmds	3.100m	17.994ms	1	1	100.00
V2	life cycle	csrng_cmds	3.100m	17.994ms	1	1	100.00
V2	stress_all	csrng_stress_all	2.017m	7.998ms	1	1	100.00
V2	intr_test	csrng_intr_test	5.000s	49.534us	1	1	100.00
V2	alert_test	csrng_alert_test	5.000s	22.657us	1	1	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	4.000s	20.614us	1	1	100.00
V2	tl_d_illegal_access	csrng_tl_errors	4.000s	20.614us	1	1	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	6.000s	20.865us	1	1	100.00
		csrng_csr_rw	4.000s	53.803us	1	1	100.00
		csrng_csr_aliasing	6.000s	36.351us	1	1	100.00
		csrng_same_csr_outstanding	5.000s	17.655us	1	1	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	6.000s	20.865us	1	1	100.00
		csrng_csr_rw	4.000s	53.803us	1	1	100.00
		csrng_csr_aliasing	6.000s	36.351us	1	1	100.00
		csrng_same_csr_outstanding	5.000s	17.655us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	tl_intg_err	csrng_sec_cm	7.000s	232.228us	1	1	100.00
		csrng_tl_intg_err	14.000s	952.604us	1	1	100.00
V2S	sec_cm_config_regwen	csrng_regwen	5.000s	19.269us	1	1	100.00
		csrng_csr_rw	4.000s	53.803us	1	1	100.00
V2S	sec_cm_config_mubi	csrng_alert	17.000s	584.436us	1	1	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	2.017m	7.998ms	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	6.000s	108.841us	1	1	100.00
		csrng_err	5.000s	39.936us	1	1	100.00
		csrng_sec_cm	7.000s	232.228us	1	1	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	6.000s	108.841us	1	1	100.00
		csrng_err	5.000s	39.936us	1	1	100.00
		csrng_sec_cm	7.000s	232.228us	1	1	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	6.000s	108.841us	1	1	100.00
		csrng_err	5.000s	39.936us	1	1	100.00
		csrng_sec_cm	7.000s	232.228us	1	1	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	6.000s	108.841us	1	1	100.00
		csrng_err	5.000s	39.936us	1	1	100.00
		csrng_sec_cm	7.000s	232.228us	1	1	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	6.000s	108.841us	1	1	100.00
		csrng_err	5.000s	39.936us	1	1	100.00
		csrng_sec_cm	7.000s	232.228us	1	1	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	6.000s	108.841us	1	1	100.00
		csrng_err	5.000s	39.936us	1	1	100.00
		csrng_sec_cm	7.000s	232.228us	1	1	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	6.000s	108.841us	1	1	100.00
		csrng_err	5.000s	39.936us	1	1	100.00
		csrng_sec_cm	7.000s	232.228us	1	1	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	17.000s	584.436us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	6.000s	108.841us	1	1	100.00
		csrng_err	5.000s	39.936us	1	1	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	2.017m	7.998ms	1	1	100.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	17.000s	584.436us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	14.000s	952.604us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	6.000s	108.841us	1	1	100.00
		csrng_err	5.000s	39.936us	1	1	100.00
		csrng_sec_cm	7.000s	232.228us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	6.000s	108.841us	1	1	100.00
		csrng_err	5.000s	39.936us	1	1	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	6.000s	108.841us	1	1	100.00
		csrng_err	5.000s	39.936us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	6.000s	108.841us	1	1	100.00
		csrng_err	5.000s	39.936us	1	1	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	6.000s	108.841us	1	1	100.00
		csrng_err	5.000s	39.936us	1	1	100.00
		csrng_sec_cm	7.000s	232.228us	1	1	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	6.000s	108.841us	1	1	100.00
		csrng_err	5.000s	39.936us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	5.000s	7.000us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			18	19	94.74

Failure Buckets

• UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started has 1 failures:
  • Test csrng_stress_all_with_rand_reset has 1 failures.

    • 0.csrng_stress_all_with_rand_reset.59119804673100598661723831985327686412281085257514094914154445314917250138793
      Line 104, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @   7000170 ps: uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer.m_edn_push_seq[1] already started
        UVM_INFO @   7000170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---