EDN Simulation Results

Thursday May 29 2025 18:32:25 UTC

GitHub Revision: 5c5f5a8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.850s	50.025us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.690s	17.435us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.710s	33.721us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	5.220s	231.427us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.890s	48.944us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.990s	21.959us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.710s	33.721us	1	1	100.00
		edn_csr_aliasing	1.890s	48.944us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	3.340s	84.997us	1	1	100.00
V2	csrng_commands	edn_genbits	3.340s	84.997us	1	1	100.00
V2	genbits	edn_genbits	3.340s	84.997us	1	1	100.00
V2	interrupts	edn_intr	1.870s	31.921us	1	1	100.00
V2	alerts	edn_alert	1.990s	76.057us	1	1	100.00
V2	errs	edn_err	1.730s	64.289us	1	1	100.00
V2	disable	edn_disable	1.770s	16.698us	1	1	100.00
		edn_disable_auto_req_mode	1.940s	88.184us	1	1	100.00
V2	stress_all	edn_stress_all	2.560s	244.972us	1	1	100.00
V2	intr_test	edn_intr_test	1.740s	21.934us	1	1	100.00
V2	alert_test	edn_alert_test	1.790s	205.722us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.560s	390.975us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.560s	390.975us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.690s	17.435us	1	1	100.00
		edn_csr_rw	1.710s	33.721us	1	1	100.00
		edn_csr_aliasing	1.890s	48.944us	1	1	100.00
		edn_same_csr_outstanding	2.370s	31.339us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.690s	17.435us	1	1	100.00
		edn_csr_rw	1.710s	33.721us	1	1	100.00
		edn_csr_aliasing	1.890s	48.944us	1	1	100.00
		edn_same_csr_outstanding	2.370s	31.339us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	4.260s	346.400us	1	1	100.00
		edn_tl_intg_err	2.780s	88.908us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.980s	34.358us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.990s	76.057us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	4.260s	346.400us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	4.260s	346.400us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	4.260s	346.400us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	4.260s	346.400us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.990s	76.057us	1	1	100.00
		edn_sec_cm	4.260s	346.400us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.990s	76.057us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.780s	88.908us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	23.090s	4.369ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00