| V1 |
smoke |
hmac_smoke |
2.220s |
86.722us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
hmac_csr_hw_reset |
1.480s |
15.125us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
hmac_csr_rw |
1.530s |
322.672us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
hmac_csr_bit_bash |
4.770s |
711.401us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
hmac_csr_aliasing |
5.180s |
757.532us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
hmac_csr_mem_rw_with_rand_reset |
2.770s |
110.853us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
hmac_csr_rw |
1.530s |
322.672us |
1 |
1 |
100.00 |
|
|
hmac_csr_aliasing |
5.180s |
757.532us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
long_msg |
hmac_long_msg |
19.620s |
16.141ms |
1 |
1 |
100.00 |
| V2 |
back_pressure |
hmac_back_pressure |
7.050s |
307.004us |
1 |
1 |
100.00 |
| V2 |
test_vectors |
hmac_test_sha256_vectors |
8.860s |
357.713us |
1 |
1 |
100.00 |
|
|
hmac_test_sha384_vectors |
6.286m |
59.315ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha512_vectors |
6.641m |
13.209ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac256_vectors |
7.960s |
238.665us |
1 |
1 |
100.00 |
|
|
hmac_test_hmac384_vectors |
8.410s |
978.608us |
1 |
1 |
100.00 |
|
|
hmac_test_hmac512_vectors |
8.780s |
988.498us |
1 |
1 |
100.00 |
| V2 |
burst_wr |
hmac_burst_wr |
2.310s |
34.101us |
1 |
1 |
100.00 |
| V2 |
datapath_stress |
hmac_datapath_stress |
6.760m |
6.663ms |
1 |
1 |
100.00 |
| V2 |
error |
hmac_error |
21.720s |
4.665ms |
1 |
1 |
100.00 |
| V2 |
wipe_secret |
hmac_wipe_secret |
1.229m |
19.705ms |
1 |
1 |
100.00 |
| V2 |
save_and_restore |
hmac_smoke |
2.220s |
86.722us |
1 |
1 |
100.00 |
|
|
hmac_long_msg |
19.620s |
16.141ms |
1 |
1 |
100.00 |
|
|
hmac_back_pressure |
7.050s |
307.004us |
1 |
1 |
100.00 |
|
|
hmac_datapath_stress |
6.760m |
6.663ms |
1 |
1 |
100.00 |
|
|
hmac_burst_wr |
2.310s |
34.101us |
1 |
1 |
100.00 |
|
|
hmac_stress_all |
4.424m |
2.680ms |
1 |
1 |
100.00 |
| V2 |
fifo_empty_status_interrupt |
hmac_smoke |
2.220s |
86.722us |
1 |
1 |
100.00 |
|
|
hmac_long_msg |
19.620s |
16.141ms |
1 |
1 |
100.00 |
|
|
hmac_back_pressure |
7.050s |
307.004us |
1 |
1 |
100.00 |
|
|
hmac_datapath_stress |
6.760m |
6.663ms |
1 |
1 |
100.00 |
|
|
hmac_wipe_secret |
1.229m |
19.705ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha256_vectors |
8.860s |
357.713us |
1 |
1 |
100.00 |
|
|
hmac_test_sha384_vectors |
6.286m |
59.315ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha512_vectors |
6.641m |
13.209ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac256_vectors |
7.960s |
238.665us |
1 |
1 |
100.00 |
|
|
hmac_test_hmac384_vectors |
8.410s |
978.608us |
1 |
1 |
100.00 |
|
|
hmac_test_hmac512_vectors |
8.780s |
988.498us |
1 |
1 |
100.00 |
| V2 |
wide_digest_configurable_key_length |
hmac_smoke |
2.220s |
86.722us |
1 |
1 |
100.00 |
|
|
hmac_long_msg |
19.620s |
16.141ms |
1 |
1 |
100.00 |
|
|
hmac_back_pressure |
7.050s |
307.004us |
1 |
1 |
100.00 |
|
|
hmac_datapath_stress |
6.760m |
6.663ms |
1 |
1 |
100.00 |
|
|
hmac_burst_wr |
2.310s |
34.101us |
1 |
1 |
100.00 |
|
|
hmac_error |
21.720s |
4.665ms |
1 |
1 |
100.00 |
|
|
hmac_wipe_secret |
1.229m |
19.705ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha256_vectors |
8.860s |
357.713us |
1 |
1 |
100.00 |
|
|
hmac_test_sha384_vectors |
6.286m |
59.315ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha512_vectors |
6.641m |
13.209ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac256_vectors |
7.960s |
238.665us |
1 |
1 |
100.00 |
|
|
hmac_test_hmac384_vectors |
8.410s |
978.608us |
1 |
1 |
100.00 |
|
|
hmac_test_hmac512_vectors |
8.780s |
988.498us |
1 |
1 |
100.00 |
|
|
hmac_stress_all |
4.424m |
2.680ms |
1 |
1 |
100.00 |
| V2 |
stress_all |
hmac_stress_all |
4.424m |
2.680ms |
1 |
1 |
100.00 |
| V2 |
alert_test |
hmac_alert_test |
1.460s |
34.249us |
1 |
1 |
100.00 |
| V2 |
intr_test |
hmac_intr_test |
1.460s |
14.663us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
hmac_tl_errors |
2.480s |
177.927us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
hmac_tl_errors |
2.480s |
177.927us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
hmac_csr_hw_reset |
1.480s |
15.125us |
1 |
1 |
100.00 |
|
|
hmac_csr_rw |
1.530s |
322.672us |
1 |
1 |
100.00 |
|
|
hmac_csr_aliasing |
5.180s |
757.532us |
1 |
1 |
100.00 |
|
|
hmac_same_csr_outstanding |
2.690s |
610.395us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
hmac_csr_hw_reset |
1.480s |
15.125us |
1 |
1 |
100.00 |
|
|
hmac_csr_rw |
1.530s |
322.672us |
1 |
1 |
100.00 |
|
|
hmac_csr_aliasing |
5.180s |
757.532us |
1 |
1 |
100.00 |
|
|
hmac_same_csr_outstanding |
2.690s |
610.395us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
17 |
17 |
100.00 |
| V2S |
tl_intg_err |
hmac_sec_cm |
1.690s |
39.231us |
1 |
1 |
100.00 |
|
|
hmac_tl_intg_err |
2.290s |
68.343us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
hmac_tl_intg_err |
2.290s |
68.343us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
| V3 |
write_config_and_secret_key_during_msg_wr |
hmac_smoke |
2.220s |
86.722us |
1 |
1 |
100.00 |
| V3 |
stress_reset |
hmac_stress_reset |
1.860s |
129.427us |
1 |
1 |
100.00 |
| V3 |
stress_all_with_rand_reset |
hmac_stress_all_with_rand_reset |
4.247m |
24.125ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
2 |
2 |
100.00 |
|
Unmapped tests |
hmac_directed |
2.640s |
57.420us |
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
28 |
28 |
100.00 |