I2C Simulation Results

Thursday May 29 2025 18:32:25 UTC

GitHub Revision: `5c5f5a8`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	23.390s	6.363ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	24.270s	1.138ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.560s	21.227us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.620s	36.001us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.940s	271.808us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.250s	524.988us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.720s	24.518us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.620s	36.001us	1	1	100.00
		i2c_csr_aliasing	2.250s	524.988us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	2.540s	135.440us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	4.392m	25.239ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	9.770s	5.199ms	1	1	100.00
V2	host_override	i2c_host_override	1.660s	27.059us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	3.221m	56.802ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	45.560s	2.759ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.830s	475.676us	1	1	100.00
		i2c_host_fifo_fmt_empty	5.430s	349.186us	1	1	100.00
		i2c_host_fifo_reset_rx	4.650s	458.967us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	42.640s	5.713ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	14.130s	423.010us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.780s	554.517us	0	1	0.00
V2	target_glitch	i2c_target_glitch	6.710s	4.088ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	2.403m	22.987ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.980s	854.864us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	47.290s	9.217ms	1	1	100.00
		i2c_target_intr_smoke	5.850s	1.163ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.310s	1.350ms	1	1	100.00
		i2c_target_fifo_reset_tx	1.790s	257.389us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	10.379m	52.231ms	1	1	100.00
		i2c_target_stress_rd	47.290s	9.217ms	1	1	100.00
		i2c_target_intr_stress_wr	22.160s	24.519ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	6.940s	2.079ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	6.940s	673.092us	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.680s	1.623ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	3.100s	2.785ms	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.540s	784.436us	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.000s	1.611ms	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	9.770s	5.199ms	1	1	100.00
		i2c_host_perf_precise	7.970s	341.555us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	14.130s	423.010us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.950s	133.714us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.860s	1.183ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.560s	1.918ms	1	1	100.00
		i2c_target_nack_txstretch	1.950s	529.474us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	11.340s	386.439us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.650s	3.130ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.510s	16.140us	1	1	100.00
V2	intr_test	i2c_intr_test	1.610s	18.060us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.000s	58.078us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.000s	58.078us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.560s	21.227us	1	1	100.00
		i2c_csr_rw	1.620s	36.001us	1	1	100.00
		i2c_csr_aliasing	2.250s	524.988us	1	1	100.00
		i2c_same_csr_outstanding	1.900s	370.295us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.560s	21.227us	1	1	100.00
		i2c_csr_rw	1.620s	36.001us	1	1	100.00
		i2c_csr_aliasing	2.250s	524.988us	1	1	100.00
		i2c_same_csr_outstanding	1.900s	370.295us	1	1	100.00
V2		TOTAL			36	38	94.74
V2S	tl_intg_err	i2c_tl_intg_err	2.530s	86.899us	1	1	100.00
		i2c_sec_cm	1.900s	352.871us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.530s	86.899us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	4.430s	477.574us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.190s	630.793us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	28.630s	1.049ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			45	50	90.00

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.108236905359192510614853754710031491058688947627523917050834799648108608569366
Line 173, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 25239282961 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @2560920

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.31702016098779105150087834791430919224526634442401427969381143572641419241249
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 630792953 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 630792953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.99759076988576384450694078996780315966001837926062744769610537417677874628108
    Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 477574488 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 477574488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:832) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.81578504808409190089533503154768554673934255419127218789864160855503770972684
    Line 95, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1049299383 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1049299383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:
- Test i2c_host_mode_toggle has 1 failures.
  - 0.i2c_host_mode_toggle.56920901511454460975747820083472193100895698704033479245428377681428559959708
    Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
```
  UVM_ERROR @ 554517367 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------
```