KEYMGR Simulation Results

Thursday May 29 2025 18:32:25 UTC

GitHub Revision: 5c5f5a8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	3.420s	520.103us	1	1	100.00
V1	random	keymgr_random	4.080s	82.521us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.640s	58.363us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.880s	45.564us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	2.270s	148.126us	0	1	0.00
V1	csr_aliasing	keymgr_csr_aliasing	7.000s	130.218us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.780s	30.387us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.880s	45.564us	1	1	100.00
		keymgr_csr_aliasing	7.000s	130.218us	1	1	100.00
V1		TOTAL			6	7	85.71
V2	cfgen_during_op	keymgr_cfg_regwen	4.370s	71.066us	1	1	100.00
V2	sideload	keymgr_sideload	28.580s	5.764ms	1	1	100.00
		keymgr_sideload_kmac	3.200s	136.139us	1	1	100.00
		keymgr_sideload_aes	6.720s	1.265ms	1	1	100.00
		keymgr_sideload_otbn	3.860s	426.853us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	3.320s	62.114us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	5.230s	499.238us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	2.980s	144.197us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	5.150s	765.646us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	3.020s	100.770us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.550s	288.658us	1	1	100.00
V2	stress_all	keymgr_stress_all	24.600s	1.498ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.650s	13.357us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.610s	34.823us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.520s	145.323us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.520s	145.323us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.640s	58.363us	1	1	100.00
		keymgr_csr_rw	1.880s	45.564us	1	1	100.00
		keymgr_csr_aliasing	7.000s	130.218us	1	1	100.00
		keymgr_same_csr_outstanding	3.580s	390.444us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.640s	58.363us	1	1	100.00
		keymgr_csr_rw	1.880s	45.564us	1	1	100.00
		keymgr_csr_aliasing	7.000s	130.218us	1	1	100.00
		keymgr_same_csr_outstanding	3.580s	390.444us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	5.420s	1.514ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	5.420s	1.514ms	1	1	100.00
		keymgr_tl_intg_err	3.560s	221.682us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	3.510s	857.731us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	3.510s	857.731us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	3.510s	857.731us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	3.510s	857.731us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	6.830s	1.102ms	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	5.420s	1.514ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	5.420s	1.514ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	3.560s	221.682us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	3.510s	857.731us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	4.370s	71.066us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	4.080s	82.521us	1	1	100.00
		keymgr_csr_rw	1.880s	45.564us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	4.080s	82.521us	1	1	100.00
		keymgr_csr_rw	1.880s	45.564us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	4.080s	82.521us	1	1	100.00
		keymgr_csr_rw	1.880s	45.564us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	5.230s	499.238us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	3.020s	100.770us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	3.020s	100.770us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	4.080s	82.521us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	9.010s	480.776us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	5.420s	1.514ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	5.420s	1.514ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	5.420s	1.514ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	3.620s	136.746us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	5.230s	499.238us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	5.420s	1.514ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	5.420s	1.514ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	5.420s	1.514ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	3.620s	136.746us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	3.620s	136.746us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	5.420s	1.514ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	3.620s	136.746us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	5.420s	1.514ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	3.620s	136.746us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	6.740s	401.415us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	30	96.67

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test keymgr_csr_bit_bash has 1 failures.

    • 0.keymgr_csr_bit_bash.35970067034340506226758886132214075802954681413928673717735428711756465993872
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[16] & 'hffffffff)))'
        UVM_ERROR @ 148126357 ps: (keymgr_csr_assert_fpv.sv:449) [ASSERT FAILED] attest_sw_binding_3_rd_A
        UVM_INFO @ 148126357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---