KMAC/MASKED Simulation Results

Thursday May 29 2025 18:32:25 UTC

GitHub Revision: 5c5f5a8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	33.630s	23.257ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.840s	65.690us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.710s	27.141us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	7.680s	1.100ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.830s	375.184us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.060s	70.504us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.710s	27.141us	1	1	100.00
		kmac_csr_aliasing	6.830s	375.184us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.580s	53.433us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.530s	39.819us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	2.948m	2.401ms	1	1	100.00
V2	burst_write	kmac_burst_write	8.962m	26.165ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	30.090s	1.424ms	1	1	100.00
		kmac_test_vectors_sha3_256	34.320s	9.383ms	1	1	100.00
		kmac_test_vectors_sha3_384	21.912m	177.120ms	1	1	100.00
		kmac_test_vectors_sha3_512	16.316m	159.406ms	1	1	100.00
		kmac_test_vectors_shake_128	26.856m	93.756ms	1	1	100.00
		kmac_test_vectors_shake_256	1.809m	7.508ms	1	1	100.00
		kmac_test_vectors_kmac	3.270s	88.197us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.200s	174.123us	1	1	100.00
V2	sideload	kmac_sideload	4.728m	20.200ms	1	1	100.00
V2	app	kmac_app	3.768m	13.532ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.675m	10.993ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	32.650s	1.077ms	1	1	100.00
V2	error	kmac_error	2.039m	52.207ms	1	1	100.00
V2	key_error	kmac_key_error	8.230s	5.044ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	7.770s	1.016ms	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	28.020s	1.562ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.870s	92.653us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	23.440s	17.760ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.290s	116.904us	1	1	100.00
V2	stress_all	kmac_stress_all	2.249m	5.009ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.630s	172.320us	1	1	100.00
V2	alert_test	kmac_alert_test	1.820s	70.855us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.620s	57.818us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.620s	57.818us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.840s	65.690us	1	1	100.00
		kmac_csr_rw	1.710s	27.141us	1	1	100.00
		kmac_csr_aliasing	6.830s	375.184us	1	1	100.00
		kmac_same_csr_outstanding	2.230s	24.678us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.840s	65.690us	1	1	100.00
		kmac_csr_rw	1.710s	27.141us	1	1	100.00
		kmac_csr_aliasing	6.830s	375.184us	1	1	100.00
		kmac_same_csr_outstanding	2.230s	24.678us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.250s	32.415us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.250s	32.415us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.250s	32.415us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.250s	32.415us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.560s	165.348us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	29.330s	9.203ms	1	1	100.00
		kmac_tl_intg_err	2.950s	423.025us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.950s	423.025us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.290s	116.904us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	33.630s	23.257ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	4.728m	20.200ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.250s	32.415us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	29.330s	9.203ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	29.330s	9.203ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	29.330s	9.203ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	33.630s	23.257ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.290s	116.904us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	29.330s	9.203ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.288m	2.787ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	33.630s	23.257ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	9.150s	120.297us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.103321503298969592920312683814446301666052729332848131605261286826249626029466
      Line 90, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 120296785 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483728 [0x80000050]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 120296785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---