KMAC/UNMASKED Simulation Results

Thursday May 29 2025 18:32:25 UTC

GitHub Revision: 5c5f5a8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	5.540s	507.436us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.740s	23.642us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.950s	34.474us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	8.210s	1.964ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.220s	1.571ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.220s	94.446us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.950s	34.474us	1	1	100.00
		kmac_csr_aliasing	8.220s	1.571ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.600s	11.760us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.850s	31.464us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	14.260m	21.401ms	1	1	100.00
V2	burst_write	kmac_burst_write	4.110m	36.675ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	33.520s	2.581ms	1	1	100.00
		kmac_test_vectors_sha3_256	17.864m	68.703ms	1	1	100.00
		kmac_test_vectors_sha3_384	19.780s	1.694ms	1	1	100.00
		kmac_test_vectors_sha3_512	10.540s	271.245us	1	1	100.00
		kmac_test_vectors_shake_128	22.090m	88.608ms	1	1	100.00
		kmac_test_vectors_shake_256	1.178m	1.639ms	1	1	100.00
		kmac_test_vectors_kmac	2.480s	60.140us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.010s	208.372us	1	1	100.00
V2	sideload	kmac_sideload	3.961m	4.639ms	1	1	100.00
V2	app	kmac_app	2.556m	10.377ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	33.220s	1.645ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.443m	5.900ms	1	1	100.00
V2	error	kmac_error	2.433m	105.142ms	1	1	100.00
V2	key_error	kmac_key_error	3.830s	1.963ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	1.460m	10.118ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	20.640s	1.958ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	22.380s	13.017ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	34.190s	4.532ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	30.160s	3.357ms	1	1	100.00
V2	stress_all	kmac_stress_all	7.690s	560.342us	1	1	100.00
V2	intr_test	kmac_intr_test	1.910s	22.187us	1	1	100.00
V2	alert_test	kmac_alert_test	1.670s	36.353us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.850s	114.757us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.850s	114.757us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.740s	23.642us	1	1	100.00
		kmac_csr_rw	1.950s	34.474us	1	1	100.00
		kmac_csr_aliasing	8.220s	1.571ms	1	1	100.00
		kmac_same_csr_outstanding	3.680s	468.634us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.740s	23.642us	1	1	100.00
		kmac_csr_rw	1.950s	34.474us	1	1	100.00
		kmac_csr_aliasing	8.220s	1.571ms	1	1	100.00
		kmac_same_csr_outstanding	3.680s	468.634us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.520s	253.701us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.520s	253.701us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.520s	253.701us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.520s	253.701us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.920s	640.076us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	46.820s	5.368ms	1	1	100.00
		kmac_tl_intg_err	3.700s	401.633us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.700s	401.633us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	30.160s	3.357ms	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	5.540s	507.436us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.961m	4.639ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.520s	253.701us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	46.820s	5.368ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	46.820s	5.368ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	46.820s	5.368ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	5.540s	507.436us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	30.160s	3.357ms	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	46.820s	5.368ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.341m	11.950ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	5.540s	507.436us	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	13.410s	579.413us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.113394128757794219728351079756829915586290213822312801063023208043113709726045
      Line 89, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10118377508 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x7597c000, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
        UVM_INFO @ 10118377508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.17780461244451602923816269087811385794426252326396740547796271685229476226994
      Line 95, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 579412664 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 579412664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---