OTBN Simulation Results

Thursday May 29 2025 18:32:25 UTC

GitHub Revision: 5c5f5a8

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	12.000s	136.054us	1	1	100.00
V1	single_binary	otbn_single	14.000s	31.799us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	46.150us	1	1	100.00
V1	csr_rw	otbn_csr_rw	6.000s	19.228us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	7.000s	120.875us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	38.214us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	9.000s	61.539us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	19.228us	1	1	100.00
		otbn_csr_aliasing	6.000s	38.214us	1	1	100.00
V1	mem_walk	otbn_mem_walk	20.000s	938.437us	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	13.000s	1.078ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	38.000s	150.485us	1	1	100.00
V2	multi_error	otbn_multi_err	44.000s	669.739us	1	1	100.00
V2	back_to_back	otbn_multi	47.000s	220.516us	1	1	100.00
V2	stress_all	otbn_stress_all	42.000s	132.124us	1	1	100.00
V2	lc_escalation	otbn_escalate	11.000s	85.856us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	7.000s	21.765us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	10.000s	75.064us	1	1	100.00
V2	alert_test	otbn_alert_test	6.000s	48.707us	1	1	100.00
V2	intr_test	otbn_intr_test	5.000s	13.969us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	33.000s	66.030us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	33.000s	66.030us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	46.150us	1	1	100.00
		otbn_csr_rw	6.000s	19.228us	1	1	100.00
		otbn_csr_aliasing	6.000s	38.214us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	17.824us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	46.150us	1	1	100.00
		otbn_csr_rw	6.000s	19.228us	1	1	100.00
		otbn_csr_aliasing	6.000s	38.214us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	17.824us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	10.000s	50.377us	1	1	100.00
		otbn_dmem_err	9.000s	50.290us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	13.000s	38.067us	1	1	100.00
		otbn_controller_ispr_rdata_err	10.000s	104.476us	1	1	100.00
		otbn_mac_bignum_acc_err	11.000s	59.427us	1	1	100.00
		otbn_urnd_err	11.000s	27.148us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	16.500us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	38.957us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	8.000s	57.485us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	8.000s	60.209us	0	1	0.00
		otbn_tl_intg_err	19.000s	62.568us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	49.000s	312.766us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	8.000s	60.209us	0	1	0.00
V2S	prim_count_check	otbn_sec_cm	8.000s	60.209us	0	1	0.00
V2S	sec_cm_mem_scramble	otbn_smoke	12.000s	136.054us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	9.000s	50.290us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	10.000s	50.377us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	19.000s	62.568us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	11.000s	85.856us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	10.000s	50.377us	1	1	100.00
		otbn_dmem_err	9.000s	50.290us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	21.765us	1	1	100.00
		otbn_illegal_mem_acc	9.000s	16.500us	1	1	100.00
		otbn_sec_cm	8.000s	60.209us	0	1	0.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	8.000s	60.209us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	otbn_single	14.000s	31.799us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	10.000s	50.377us	1	1	100.00
		otbn_dmem_err	9.000s	50.290us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	21.765us	1	1	100.00
		otbn_illegal_mem_acc	9.000s	16.500us	1	1	100.00
		otbn_sec_cm	8.000s	60.209us	0	1	0.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	8.000s	60.209us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	11.000s	85.856us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	10.000s	50.377us	1	1	100.00
		otbn_dmem_err	9.000s	50.290us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	21.765us	1	1	100.00
		otbn_illegal_mem_acc	9.000s	16.500us	1	1	100.00
		otbn_sec_cm	8.000s	60.209us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	8.000s	60.209us	0	1	0.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	14.000s	31.799us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	11.000s	74.129us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	32.721us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	30.000s	191.020us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	30.000s	191.020us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	10.000s	33.002us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	8.000s	60.209us	0	1	0.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	8.000s	60.209us	0	1	0.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	9.000s	222.467us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	8.000s	60.209us	0	1	0.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	8.000s	60.209us	0	1	0.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	12.000s	25.804us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	12.000s	25.804us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	9.000s	19.360us	0	1	0.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	14.000s	31.799us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	14.000s	31.799us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	14.000s	31.799us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	47.000s	220.516us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	14.000s	31.799us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	14.000s	31.799us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	9.000s	25.226us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	14.000s	31.799us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	8.000s	60.209us	0	1	0.00
V2S		TOTAL			18	20	90.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	1.467m	2.095ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	41	92.68

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:929) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 0.otbn_stress_all_with_rand_reset.71113820509976512620965899218920238888884126257588186131006300854728273323376
      Line 278, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2094860245 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2094860245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:

  • Test otbn_sec_wipe_err has 1 failures.

    • 0.otbn_sec_wipe_err.47436349395022785051153851755297247804283193212627940501989171584461363716925
      Line 107, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 19360413 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
        UVM_ERROR @  19360413 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @  19360413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 1 failures:

  • Test otbn_sec_cm has 1 failures.

    • 0.otbn_sec_cm.64956268654009134370908859697665019704183541533867558654149342788554494851314
      Line 96, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 60208605 PS) Assertion tb.dut.ErrBitsKnown_A has failed
        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 60208605 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
        UVM_ERROR @  60208605 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
        UVM_INFO @  60208605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---