PATTGEN Simulation Results

Thursday May 29 2025 18:32:25 UTC

GitHub Revision: 5c5f5a8

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	3.000s	68.760us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	4.000s	17.280us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	4.000s	22.489us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	70.230us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	4.000s	90.949us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	14.512us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	4.000s	22.489us	1	1	100.00
		pattgen_csr_aliasing	4.000s	90.949us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	2.767m	45.543ms	1	1	100.00
V2	cnt_rollover	cnt_rollover	11.000s	4.156ms	1	1	100.00
V2	error	pattgen_error	4.000s	117.091us	1	1	100.00
V2	stress_all	pattgen_stress_all	3.000s	67.443us	1	1	100.00
V2	alert_test	pattgen_alert_test	4.000s	27.270us	1	1	100.00
V2	intr_test	pattgen_intr_test	4.000s	14.535us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	4.000s	101.328us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	4.000s	101.328us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	4.000s	17.280us	1	1	100.00
		pattgen_csr_rw	4.000s	22.489us	1	1	100.00
		pattgen_csr_aliasing	4.000s	90.949us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	15.537us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	4.000s	17.280us	1	1	100.00
		pattgen_csr_rw	4.000s	22.489us	1	1	100.00
		pattgen_csr_aliasing	4.000s	90.949us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	15.537us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	151.567us	1	1	100.00
		pattgen_sec_cm	4.000s	237.871us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	151.567us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	29.000s	2.985ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	4.000s	55.743us	1	1	100.00
		TOTAL			17	18	94.44

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:929) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test pattgen_stress_all_with_rand_reset has 1 failures.

    • 0.pattgen_stress_all_with_rand_reset.109131618628171191874800311970986607395573842871266076856710929699322847545825
      Line 118, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1227194851 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 1227202246 ps: (cip_base_vseq.sv:833) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 1227202246 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
        Issuing reset for run 1/10
        UVM_INFO @ 1227237541 ps: (cip_base_vseq.sv:857) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]