ROM_CTRL/32KB Simulation Results

Thursday May 29 2025 18:32:25 UTC

GitHub Revision: 5c5f5a8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 5.120s 814.253us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 6.090s 166.807us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 5.580s 164.330us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 8.110s 539.666us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 5.710s 124.401us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 5.220s 177.488us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 5.580s 164.330us 1 1 100.00
rom_ctrl_csr_aliasing 5.710s 124.401us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 5.590s 299.062us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 5.910s 165.466us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 5.680s 319.018us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 14.300s 418.472us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 7.360s 278.899us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.590s 292.051us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 8.890s 536.120us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 8.890s 536.120us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 6.090s 166.807us 1 1 100.00
rom_ctrl_csr_rw 5.580s 164.330us 1 1 100.00
rom_ctrl_csr_aliasing 5.710s 124.401us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.340s 130.227us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 6.090s 166.807us 1 1 100.00
rom_ctrl_csr_rw 5.580s 164.330us 1 1 100.00
rom_ctrl_csr_aliasing 5.710s 124.401us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.340s 130.227us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.048m 6.154ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 13.230s 3.286ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 3.752m 3.249ms 1 1 100.00
rom_ctrl_tl_intg_err 43.190s 371.527us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 3.752m 3.249ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 3.752m 3.249ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.048m 6.154ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.048m 6.154ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.048m 6.154ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.048m 6.154ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.048m 6.154ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 3.752m 3.249ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 3.752m 3.249ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 5.120s 814.253us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 5.120s 814.253us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 5.120s 814.253us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 43.190s 371.527us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.048m 6.154ms 1 1 100.00
rom_ctrl_kmac_err_chk 7.360s 278.899us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.048m 6.154ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.048m 6.154ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.048m 6.154ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 13.230s 3.286ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 3.752m 3.249ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 18.680s 1.173ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00