ROM_CTRL/64KB Simulation Results

Thursday May 29 2025 18:32:25 UTC

GitHub Revision: 5c5f5a8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 8.940s 640.995us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 7.360s 1.316ms 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 7.100s 554.256us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 7.350s 535.022us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 7.800s 298.230us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 7.300s 223.038us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 7.100s 554.256us 1 1 100.00
rom_ctrl_csr_aliasing 7.800s 298.230us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 6.290s 726.659us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 6.440s 1.413ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 8.620s 392.514us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 28.510s 775.054us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 11.830s 1.426ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 6.730s 1.412ms 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 14.030s 303.629us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 14.030s 303.629us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 7.360s 1.316ms 1 1 100.00
rom_ctrl_csr_rw 7.100s 554.256us 1 1 100.00
rom_ctrl_csr_aliasing 7.800s 298.230us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.990s 675.330us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 7.360s 1.316ms 1 1 100.00
rom_ctrl_csr_rw 7.100s 554.256us 1 1 100.00
rom_ctrl_csr_aliasing 7.800s 298.230us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.990s 675.330us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 2.018m 14.515ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 26.570s 1.074ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.830m 461.420us 1 1 100.00
rom_ctrl_tl_intg_err 1.087m 330.278us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.830m 461.420us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.830m 461.420us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.018m 14.515ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.018m 14.515ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.018m 14.515ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.018m 14.515ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.018m 14.515ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.830m 461.420us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.830m 461.420us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 8.940s 640.995us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 8.940s 640.995us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 8.940s 640.995us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.087m 330.278us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.018m 14.515ms 1 1 100.00
rom_ctrl_kmac_err_chk 11.830s 1.426ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 2.018m 14.515ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 2.018m 14.515ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 2.018m 14.515ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 26.570s 1.074ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.830m 461.420us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.244m 1.792ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00