RV_TIMER Simulation Results

Thursday May 29 2025 18:32:25 UTC

GitHub Revision: 5c5f5a8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.480s	12.246us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.530s	22.088us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.520s	13.735us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.190s	573.490us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.740s	34.252us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.610s	22.053us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.520s	13.735us	1	1	100.00
		rv_timer_csr_aliasing	1.740s	34.252us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.550s	17.375us	1	1	100.00
V2	disabled	rv_timer_disabled	1.730s	964.955us	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	1.610s	229.000us	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	1.610s	229.000us	1	1	100.00
V2	stress	rv_timer_stress_all	1.960s	399.632us	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.420s	42.547us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.440s	73.591us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.150s	208.725us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.150s	208.725us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.530s	22.088us	1	1	100.00
		rv_timer_csr_rw	1.520s	13.735us	1	1	100.00
		rv_timer_csr_aliasing	1.740s	34.252us	1	1	100.00
		rv_timer_same_csr_outstanding	1.560s	24.229us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.530s	22.088us	1	1	100.00
		rv_timer_csr_rw	1.520s	13.735us	1	1	100.00
		rv_timer_csr_aliasing	1.740s	34.252us	1	1	100.00
		rv_timer_same_csr_outstanding	1.560s	24.229us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.700s	701.149us	1	1	100.00
		rv_timer_tl_intg_err	1.900s	111.762us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.900s	111.762us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	24.360s	8.781ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.470s	47.156us	1	1	100.00
		rv_timer_max	1.450s	13.310us	1	1	100.00
		TOTAL			19	19	100.00