SPI_DEVICE/1R1W Simulation Results

Thursday May 29 2025 18:32:25 UTC

GitHub Revision: 5c5f5a8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	3.005m	26.757ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.020s	22.918us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.790s	59.200us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	10.060s	320.257us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	17.470s	2.975ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.280s	201.546us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.790s	59.200us	1	1	100.00
		spi_device_csr_aliasing	17.470s	2.975ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.620s	44.864us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.280s	66.071us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.810s	26.865us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.650s	1.378us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.960s	4.641us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.820s	32.644us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.820s	32.644us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	4.330s	4.613ms	1	1	100.00
		spi_device_tpm_sts_read	1.820s	164.483us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	10.980s	1.443ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	2.760s	143.470us	1	1	100.00
		spi_device_flash_all	1.170m	14.247ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	4.620s	1.946ms	1	1	100.00
		spi_device_flash_all	1.170m	14.247ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	4.620s	1.946ms	1	1	100.00
		spi_device_flash_all	1.170m	14.247ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.170m	14.247ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	8.580s	3.011ms	1	1	100.00
		spi_device_flash_all	1.170m	14.247ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	8.580s	3.011ms	1	1	100.00
		spi_device_flash_all	1.170m	14.247ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	8.580s	3.011ms	1	1	100.00
		spi_device_flash_all	1.170m	14.247ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	8.580s	3.011ms	1	1	100.00
		spi_device_flash_all	1.170m	14.247ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	8.580s	3.011ms	1	1	100.00
		spi_device_flash_all	1.170m	14.247ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	5.660s	3.466ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	37.960s	7.421ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	37.960s	7.421ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	37.960s	7.421ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	5.420s	743.545us	1	1	100.00
		spi_device_read_buffer_direct	17.730s	2.099ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	37.960s	7.421ms	1	1	100.00
		spi_device_flash_all	1.170m	14.247ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.170m	14.247ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.170m	14.247ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.770s	284.263us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.770s	284.263us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	3.005m	26.757ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	15.620s	10.544ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.704m	26.731ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.530s	16.900us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.780s	38.084us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.380s	108.552us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.380s	108.552us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.020s	22.918us	1	1	100.00
		spi_device_csr_rw	2.790s	59.200us	1	1	100.00
		spi_device_csr_aliasing	17.470s	2.975ms	1	1	100.00
		spi_device_same_csr_outstanding	2.690s	360.947us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.020s	22.918us	1	1	100.00
		spi_device_csr_rw	2.790s	59.200us	1	1	100.00
		spi_device_csr_aliasing	17.470s	2.975ms	1	1	100.00
		spi_device_same_csr_outstanding	2.690s	360.947us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.940s	312.789us	1	1	100.00
		spi_device_tl_intg_err	10.350s	406.629us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	10.350s	406.629us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.241m	90.709ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.113534761440691396493428133824607626460510666809428124935881318365499120470402
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1242263 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[72])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1242263 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1242263 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[968])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.70305709391860276836193054613299611646002973967136130799896112208072904159765
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   2237888 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x57e89b [10101111110100010011011] vs 0x0 [0])
        UVM_ERROR @   2328888 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x27f5f4 [1001111111010111110100] vs 0x0 [0])
        UVM_ERROR @   2376888 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xadff3d [101011011111111100111101] vs 0x0 [0])
        UVM_ERROR @   2455888 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x43034 [1000011000000110100] vs 0x0 [0])
        UVM_ERROR @   2502888 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x75d693 [11101011101011010010011] vs 0x0 [0])