SPI_DEVICE/2P Simulation Results

Thursday May 29 2025 18:32:25 UTC

GitHub Revision: 5c5f5a8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	2.836m	118.254ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.870s	22.151us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.510s	66.288us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	23.870s	1.881ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	17.150s	2.333ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.710s	559.097us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.510s	66.288us	1	1	100.00
		spi_device_csr_aliasing	17.150s	2.333ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.800s	23.309us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.310s	44.771us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.700s	19.840us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.960s	245.861us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	1.680s	131.803us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	1.650s	24.838us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.650s	24.838us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	11.790s	4.728ms	1	1	100.00
		spi_device_tpm_sts_read	1.600s	25.738us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	9.020s	2.024ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	19.240s	41.165ms	1	1	100.00
		spi_device_flash_all	35.710s	8.953ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	2.890s	106.779us	1	1	100.00
		spi_device_flash_all	35.710s	8.953ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	2.890s	106.779us	1	1	100.00
		spi_device_flash_all	35.710s	8.953ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	35.710s	8.953ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.770s	1.161ms	1	1	100.00
		spi_device_flash_all	35.710s	8.953ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.770s	1.161ms	1	1	100.00
		spi_device_flash_all	35.710s	8.953ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.770s	1.161ms	1	1	100.00
		spi_device_flash_all	35.710s	8.953ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.770s	1.161ms	1	1	100.00
		spi_device_flash_all	35.710s	8.953ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.770s	1.161ms	1	1	100.00
		spi_device_flash_all	35.710s	8.953ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	6.830s	979.628us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	17.180s	14.112ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	17.180s	14.112ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	17.180s	14.112ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	12.500s	1.031ms	1	1	100.00
		spi_device_read_buffer_direct	8.300s	634.503us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	17.180s	14.112ms	1	1	100.00
		spi_device_flash_all	35.710s	8.953ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	35.710s	8.953ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	35.710s	8.953ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	16.610s	18.311ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	16.610s	18.311ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	2.836m	118.254ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.807m	17.710ms	1	1	100.00
V2	stress_all	spi_device_stress_all	2.120s	90.230us	1	1	100.00
V2	alert_test	spi_device_alert_test	1.670s	13.285us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.640s	39.191us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.740s	90.437us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.740s	90.437us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.870s	22.151us	1	1	100.00
		spi_device_csr_rw	2.510s	66.288us	1	1	100.00
		spi_device_csr_aliasing	17.150s	2.333ms	1	1	100.00
		spi_device_same_csr_outstanding	3.770s	170.528us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.870s	22.151us	1	1	100.00
		spi_device_csr_rw	2.510s	66.288us	1	1	100.00
		spi_device_csr_aliasing	17.150s	2.333ms	1	1	100.00
		spi_device_same_csr_outstanding	3.770s	170.528us	1	1	100.00
V2		TOTAL			22	22	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.910s	91.917us	1	1	100.00
		spi_device_tl_intg_err	12.000s	580.596us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	12.000s	580.596us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	34.100s	11.055ms	1	1	100.00
		TOTAL			33	33	100.00