SRAM_CTRL/MAIN Simulation Results

Thursday May 29 2025 18:32:25 UTC

GitHub Revision: 5c5f5a8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	33.960s	1.220ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.090s	17.302us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.520s	35.090us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.840s	29.118us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.880s	19.198us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.730s	1.433ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.520s	35.090us	1	1	100.00
		sram_ctrl_csr_aliasing	1.880s	19.198us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.909m	7.142ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	51.490s	4.146ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	4.575m	46.546ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.027m	3.254ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	14.452m	272.461ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	8.302m	11.554ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	27.750s	7.152ms	1	1	100.00
V2	executable	sram_ctrl_executable	4.091m	48.560ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	37.360s	8.118ms	1	1	100.00
		sram_ctrl_partial_access_b2b	5.112m	7.647ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	47.330s	1.558ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	53.280s	3.401ms	1	1	100.00
		sram_ctrl_throughput_w_readback	28.270s	1.754ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	3.724m	6.082ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.570s	1.406ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	29.913m	55.963ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.480s	19.400us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.050s	349.042us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.050s	349.042us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.090s	17.302us	1	1	100.00
		sram_ctrl_csr_rw	1.520s	35.090us	1	1	100.00
		sram_ctrl_csr_aliasing	1.880s	19.198us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.700s	49.753us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.090s	17.302us	1	1	100.00
		sram_ctrl_csr_rw	1.520s	35.090us	1	1	100.00
		sram_ctrl_csr_aliasing	1.880s	19.198us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.700s	49.753us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	39.400s	29.376ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.770s	5.084us	0	1	0.00
		sram_ctrl_tl_intg_err	2.230s	179.663us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.770s	5.084us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.230s	179.663us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	3.724m	6.082ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	3.724m	6.082ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.520s	35.090us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	4.091m	48.560ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	4.091m	48.560ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	4.091m	48.560ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	27.750s	7.152ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	7.410s	2.907ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	39.400s	29.376ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.950s	3.330ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	33.960s	1.220ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	33.960s	1.220ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	4.091m	48.560ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.770s	5.084us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	27.750s	7.152ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.770s	5.084us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.770s	5.084us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	33.960s	1.220ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.770s	5.084us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	32.010s	4.214ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.81394973124619973814503188550959105486264329881762254605159278330020030679174
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   5083946 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   5083946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---